IEEE Circuits and Systems Magazine - Q1 2020 - 21

capacitance from the circuit [58]. Therefore, the RGC-TIA
is widely used in many literatures because of its low input
impedance that is achievable at a relatively low power consumption [59]-[65]. By analyzing the small signal model,
the transimpedance gain is obtained and it is given by:
(G m ron + 1) R D
(32a)
(SC out R D + 1) (SC PD (R D + ron) + G m ron + 1)
(32b)
Z (0) TIA = R D

Z (S ) TIA =

where G m is the effective transconductance of the cascode stage described by:
G m = g mn ( ; A rg ; + 1)

(33)

where A rg is the voltage gain of the regulating amplifier
which is presented by:
A rg = - g mnrg (ronrg //R rg)

(34)

The zero frequency input resistance is given by:
Z (0) in =

R D + ron
- 1
G mn ron + 1 G mn

(35)

Assuming that the dominant pole is resulted from
C PD and Z (0) in, then the BW is described by:
BW =

G mn ron + 1
- G mn
2rC PD (R D + ron) 2rC PD

(36)

Equation (33) clearly shows an ( ; A rg ; + 1) enhancement of the transconductance compared to the CG-TIA.
Therefore, the BW is increased at the same transimpedance gain and a higher GBW can be obtained.
The total input referred noise current of the RGC-TIA
is demonstrated by equation (37) where g mnB is the transconductance of the biasing current source transistor, R D
and M n noise contribution is described by the first and
second term respectively. The third term is the noise contribution of the biasing current source NMOS, the fourth
term is the noise contribution of the regulating amplifier.
Equation (37) also reveals that the noise of the biasing current source transistor is directly referred to the
input. Accordingly, the total integrated input noise current of the RGC-TIA is expected to be higher compared to
its closed loop topologies counterparts. However, since
the transconductance is higher by a factor ( ; A rg ; + 1), the
noise performance of the RGC-TIA is expected to be better than the CG-TIA at low frequencies.
I 2n, in = 4K B T =

2

2

(2rf C in ron) + (G m ron) + 1
RD
(1 + G m ron) 2
(2rf C in ron)2
+
g m c n + g mnB c n
(1 + G m ron)2
(2rf C PD g mn ron (R rg //ronrg)) 2
1 G
+
c g mnrg c n +
m
R rg
(1 + G m ron) 2
(37)

FIRST QUARTER 2020

It should be clarified that to obtain a high transimpedance gain and 5 KHz BW, the value of R D must be increased to an order of multiple MOhms. Consequently,
the biasing current source I B must be less than 100 nA
to allow reasonable voltage headroom which forces the
NMOS to work in the subthreshold region. Thus, open
loop topologies like CG-TIA and RGC-TIA are preferred in
high BW designs like FD-NIRS and time domain near infrared spectroscopy (TD-NIRS) and are rarely used in low
BW applications (PPG sensors). Also, the trade-off between
the noise and the power consumption is not presented, as
the same as in the case of the CG-TIA. Simulation parameters used for simulating the RGC-TIA are listed in table VI.
G. Current Reuse TIA (CR-TIA)
The schematic diagram of the CR-TIA is shown in Fig. 10.
The topology is consisted of a common source amplifier
with a shunt-shunt feedback (M n1, R F ) forming a CS-TIA.
The CS-TIA is followed by a common gate stage (M n2,
M p). First, the input current is fed to the CS-TIA, then,
the output voltage of the CS-TIA is fed to the common
gate stage for further amplification. Therefore, the input is amplified two times using the same DC biasing
current which reduces the power consumption (current reuse). Nevertheless, smaller voltage headroom
is attained per transistor which degrades the linearity
compared to the CS-TIA.

Table VI.
Simulation parameters of the RGC-TIA.
Case

WMn

RD

Rrg

WMnrg

5 KHz

10 μm

16.2 MΩ

80 K Ω

1 μm

100 MHz

30 μm

19 KΩ

5 KΩ

5 μm

VDD
VB2

Mp
Vout

VB1
IPD

Mn2

CPD
RF
Mn1

Figure 10. Schematic diagram of the CR-TIA.

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IEEE Circuits and Systems Magazine - Q1 2020

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