IEEE Circuits and Systems Magazine - Q1 2020 - 28

Input Noise Spectral Density (pA /√Hz)

referred noise. However, higher transimpedance gain inherently limits I Ovl
p - p which degrades the linearity and the
dynamic range of the relatively higher open loop gain TIAs.
The CR-TIA and CR-RGC-TIA topologies achieves a higher GBW and FoM 1 compared to the CS-TIA. On the other
hand, CS-TIA attains lower power consumption and better
DR at the same achievable input referred noise current.
It is clear that the CG-TIA and the RGC-TIA are a very
appealing choice when low power consumption is the
main designer's concern. Clearly shown by the results,
RGC-TIA noticeably outperforms all other topologies
when minimizing the power consumption is the major
goal. This superiority is obtained due to the high achievable effective transconductance of the cascode transistor at a relatively low DC biasing current. Thus, it is rec-

14
12
10
8
6
4
2
0
100

10 K 100 K 1 M 10 M 100 M 1,000 M
Frequency (Hz)
CS-TIA
Inv-TIA
InvCas-TIA
RIC-TIA

CG-TIA
CR-TIA
CR-RGC-TIA
RGC-TIA

Figure 19. Input noise current spectral density of the reviewed TIAs while targeting min power and 100 MHz BW.

ommended to use the RGC-TIA if the noise performance
requirements are not very constrained and the design
has to be efficient in term of the power consumption,
e.g., implantable devices.
IV. Conclusions
In this work, various state of the art TIAs mentioned in
the literatures are outlined, analyzed, simulated, and
compared. A noise and transimpedance gain mathematical models of all of the reviewed topologies are listed
and discussed. For the first time, these studied topologies are simulated altogether at four different cases to
account for a variety of design requirements and to allow a reasonable comparison methodology. The study
outlined that for closed loop topologies, the higher the
open loop gain, the higher the performance according to
the figure of merit, FoM 1 described in this paper. This
study also suggests that using transconductance boosting techniques like inverter based cascode and regulating cascode stages can greatly boosts the GBW performance of the TIA and reduces its input referred noise.
The InvCas-TIA and the RIC-TIA generally show great
performance in terms of GBW, low input referred noise
current, and low power consumption. Those two topologies are strongly recommended if the application sensitivity is of the major concern and they are optimized for minimum input referred noise. Moreover, both can achieve
a relatively low power consumption while having a high
open loop gain, thus, they can attain high transimpedance
gain. Those aspects make both topologies very attractive
for most of the biomedical applications. However, both topologies are not the best in terms of the DR especially at
low power consumption.
On the other hand, CR-TIA and CR-RGC-TIA shows superiority over the CS-TIA in terms of GBW and FoM 1 at
the expense of linearity, noise, and hence, the DR. In addition, the comparison shows that the noise performance

Table XII.
A comparison between the reviewed TIA topologies at CPD = 2 pF and 100 MHz BW while targeting minimum power.

Topology

Gain
(dBΩ)

BW
(MHz)

Total Integrated
Input Noise nA rms

Power
μW

I Ovl
p -p
μA p -p

DR
(dB)

FoM1

FoM2

CS-TIA

65.7

100

104.3

64.8

1167.2

Inv-TIA

71.6

100

143.7

62.7

92.8

7241

InvCas-TIA

77.1

100

101.3

9.4

44.3

248.1

2331.7

RIC-TIA

79.2

100

109

2.3

32.1

293.6

675.2

CR-TIA

100

188

1.1

25.7

117.8

129.5

CR-RGC-TIA

77.7

100

162

0.38

16.5

166.2

63.2

CG-TIA

100

45.8

100

61.6

173.8

9561.5

RGC-TIA

85.5

100

41.6

100

54.1

905.6

19017.6

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IEEE Circuits and Systems Magazine - Q1 2020

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