IEEE Circuits and Systems Magazine - Q1 2020 - 54

Adaptation proves to be a tool that should be mastered
in practical applications to unleash the full
potential of compressed sensing.
the voltage level to be provided as circuit output. After
n integration time steps, and assuming C s = C f , we get at
the circuit output
n-1

/ a k x (k0) = a < x (0) = y (0)

k=0

that is the measurement associated to the generic row
a < for the time windows I 0 .
As final step, in both the considered cases (i.e., when
x (t ) is high-frequency and measurements are computed by means of a continuous-time integrator [47], [48],
and when x (t ) is low-frequency and measurements are
achieved with a switched capacitor integrator [37], [49],
[51]) y is finally converted in digital words by a proper
ADC (represented by the Q ($) function of Figure 9) operating at a sub-Nyquist rate6.
Another group of works [50], [52] assume to operate directly on digital input signals. This approach has recently
been receiving increasing attention, and aims at using
CS as an early digital processing stage replacing complex and expensive (either in terms of required energy
or hardware resources) classic compression algorithms.
The corresponding architecture is shown as the "digital"
case in Figure 9. The vector x is made of digital words after windowing, sampling and quantizing the input signal
x (t ). In order to compute y, it is enough to process x with
a common digital MAC architecture. Even if, in this case,
the measurement y is already a digital quantity that can
be delivered "as is" to the reconstruction algorithm, it is
a common practice to apply an additional re-quantization
function (such as the Ql ($) in the figure) to ensure, for
example, a better adaptation to the statistics of y.
B. Multiplication by a k
Notwithstanding the actual implementation as a multiply-and-integrate [47], [48], or a as multiply-and-accumulate stage [37], [49]-[51], [53], one of the main difficulties
in realizing a CS signal acquisition stage is multiplying
the input signal by the sensing sequence/function. In
fact, a multiplier is one of the most complicated circuital
block in a signal processing chain, both in the analog
and in the digital domain.
To tackle this issue, almost all the considered works
constrains the elements of vectors a k to assume a very
6
While the Nyquist rate is defined as n/Tw, with this solution the ADC is
working at a rate given by 1/Tw, or m/Tw in case a single shared ADC is
used to convert all m measurements.

54

IEEE CIRCUITS AND SYSTEMS MAGAZINE

limited number of values. In [37], [47]-[49], it is required
that a k ! {-1, +1}. The advantage of this approach is
clear: the multiplier block can be replaced by a simple
sign inversion circuit. More specifically, in the analog
domain, and assuming a differential encoding for x (t )
[37], [47]-[49], [51], a few pass transistors capable of exchanging the x +(t ) and x -(t ) line are enough to perform
multiplication by -1. In the digital domain, the solution
is similarly simple since a straightforward two's complement allows a multiplication by -1. The multiplication
by +1 is, of course, trivial in both cases.
Another possible solution is to ask that a k ! {0, +1}
[50], [51], [53]. In this case the situation is even simpler, since the multiplication by +1 or 0 is simply
achieved by allowing the input signal to be summed/
integrated or by disconnecting it from the rest of the
circuit, respectively.
When multiplication by an arbitrary value is desired, the resulting circuit complexity is expected to
substantially increase and several authors have proposed remedies to cope with this. As an example, in
the discrete-time analog input signal case, the authors
of [49] describe a solution to achieve the multiplication
by a 6-bit integer value at virtually no cost in terms of
energy. More specifically, instead of relying on a simple
switched capacitor integrator based on two capacitors
such that shown in the "analog discrete-time" case of
Figure 9, they replace C s with a 5-bit C-2C split capacitor array circuit typically used in digital-to-analog converter. The effect is that only a part (that is proportional
to the 5-bits control value) of the charge accumulated
on the C-2C split capacitor array is transferred to the C f ,
thus performing at the same time both a multiplication
and the integration without any additional active device.
The 6-th bit of the control word is used as sign bit, and
decides if the signal to be integrated is x (t ) or - x (t ) by
exchanging the x +(t ) and x -(t ) differential lines.
C. Time Continuity
In the windowing approach illustrated so far, the input
signal x (t ) is sliced with respect to contiguous and non
overlapping time intervals of length Tw . From a circuital
point of view, let us refer again to Figure 9 and consider
the time interval I (l ). The measurement y (l ) is computed
by considering the input signal slice x (l )(t ) and a. At
the end of I (l ), y (l ) is available, and can be converted
into a digital word (or requantized assuming a digital
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