IEEE Circuits and Systems Magazine - Q1 2020 - 55

Adapted CS is definitely worth pursuing whenever designing the
low-resources, autonomous, ubiquitous sensing subsystems
that will be the backbone of future IoT applications.
architecture). After that, the integrator circuit have to
be reset in order to be ready to start the computation
of a new measurement y (l + 1). Note that these two operations (conversion to digital word/requantization and reset) may require a non-negligible amount of time.
Yet, at the same time instant when I (l ) ends, I (l + 1)
starts and all the aforementioned processes need to be
repeated on the successive slice x (l + 1)(t ) of the input
signal to compute y (l + 1). While it is reasonable to assume that both y (l ) and y (l +1) should be computed by
the same hardware block, it is straightforward to understand that the two above requirements are conflicting:
i ) a certain amount of time is needed for the hardware
block to be ready for start the computation of the new
measurement, and ii ) the computation of the new measurement should start immediately after the end of the
elaboration of the previous one.
While the solution for a digital architecture is trivial
(a latch is enough to store the accumulated value so that
the multiply-and-accumulate block is ready for the next
computation), the situation is more complicated when
considering analog hardware. In the latter case, a complex (and energy-hungry) analog sample/hold should in
principle be required. To avoid it, [48] and [37] propose
two similar solutions to be applied to the continuoustime and the discrete-time model, respectively.
Referring to the "analog continuous-time" case of Figure 9, in [48] the proposed multiply-and-integrate block
is composed by a single multiplication block and by two
integration paths. When the first block is integrating,
the second one is disconnected from the multiplier and
is working as a sample/hold block. This allows enough
time to the cascade circuit to digitize the results, and
also to clear the charge accumulated on C f before starting a new integration. At the end of the time window, the
role of the two paths is exchanged: the first one works
as a sample/hold, while the second path starts a new
integration phase for computing the next measurement.
An even simpler solution is presented in [37], where
the proposed design is based on a switched capacitor architecture. Referring to the circuit sketched in the "analog
discrete-time" case of Figure 9, the authors created two
integration paths by replicating only the feedback capacitors C f , while all other element (the multiplier, C s and the
active amplifier) are shared. The working principle is exactly the same as in the previous case: when the first C f is
used for computing the actual measurement, the second
FIRST QUARTER 2020

C f is sampling the previous measurement and may be
connected to the cascading analog-to-digital converter,
leaving enough time for the conversion and for removing the charge accumulated on it. At the end of each time
window, the role of the two capacitors is exchanged. Note
also that the further advantage of this solution is that no
active (and so, energy consuming) devices are replicated.
D. Saturation
Independently of the architecture, measurements must be
quantized/requantized before dispatching them. Unfortunately, such an operation may lead to saturation problems.
Even if this has been rarely considered, it is a severe issue
both for analog and digital CS implementations.
Since y = / nk -=10 a k x k, and assuming a large n (or more
precisely, assuming that the number of terms a k x k ! 0
is large), the central limit theorem can be applied to the
sum resulting into y. As a consequence, the distribution
of the result is expected to be approximately Gaussian,
so that y may indeed assume very large values, while
the majority of the observed cases will be practically
located around the mean value.
This is an important issue for a twofold reason: i ) the
applied quantization function is uniform, i.e., all quantization steps have the same size, and ii ) the conversion range is limited by an upper and a lower threshold,
which identify the interval where conversion is correctly preformed, while outside it saturation occurs.
When an analog CS architecture needs to be implemented, the two above mentioned quantization thresholds must carefully be selected. In fact, it is obvious that
using very different values can decrease (ideally, down
to zero) the probability of a saturation event. This has
however the drawback, due to the large quantization
step, to increase the quantization error and reduces the
reconstruction quality. Conversely, making the values of
the two thresholds closer to each other results in a lower quantization error, but increases to a non-negligible
value the probability of a saturation event.
A similar problem has to be considered also when
computing y by means of a digital multiply-and-accumulate block. Unless a complex and non-efficient floating point representation is used, a high number of bits in
the representation of y will result in negligible probability of saturation. The drawback is the non-efficient coding, since the most significant bits will hardly ever be
used. It is worth stressing that a non-efficient coding of
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