IEEE Circuits and Systems Magazine - Q2 2020 - 11
is p
- lesiochronous distribution hierarchy (PDH) where
multiple PRCs (primary reference clock, a frequency
source of high stability, typically at +10 -11 ) are distributed
independently among the nodes [20], as shown in the left
of figure 2. On the right is the master-slave method where a
high-quality PRC functions as the source. It is then distributed to slave nodes through electrical or optical channels
(passing signal as a train of pulses). This task is usually
assisted by special frequency-lock circuit such as phase
locked loop (PLL). This approach is used in Synchronous
Digital Hierarchy (SDH) [20].
Phase and time synchronizations however require a
method of transfer. TDM networks have timing transfer
capability inherently built into them. Packet networks
(e.g. Ethernet, IP, MPLS) is naturally asynchronous
and was not designed with timing transfer in mind.
Using TDM-like timing techniques, Synchronous Ethernet (Sync-E) has emerged as a powerful and simple
technology for accurate timing transfer over Ethernet
networks. In packet network, there are two ways to
transport timing information. In Figure 3, a dedicated
bit stream of CBR (constant bit rate) is used to link the
PHYs in transmitter and receiver.
CDR (clock data recovery) circuit is then used in the receiver
Master-Slave
Plesiochronous
to extract the timing information
PRC
PRC
f1 ≈ f
Master
f
embedded in the stream [21]. In
another way, as shown in figPRC
PRC
fj ≈ f
f2 ≈ f
SSU
f
ure 4, a high level feedback conf
SSU
SSU
trol loop is used to extract freNode
PRC
f
fi ≈ f
quency from the incoming packet
(Slave)
SSU:
[22]. After frequency link is estabSynchronization
PRC: Primary Reference Clock
Supply Unit
lished over the packet network,
phase and time are derived from
Figure 2. Frequency synchronization: plesiochronous (left) and master-slave (right).
it using protocols and algorithms.
Receiver Node
Transmitter Node
Transmit
PHY
PRC
CBR
PLL
CBR: Constant Bit Rate
CDR: Clock Data Recovery
PLL: Phase Locked Loop
Receiver
PHY
Clock
(Traceable to PRC)
PLL
CDR
Figure 3. Frequency transport in packet network: through CBR and CDR.
Receiver (A Node in the Network)
Packet
Timing
Signal
Prefiltering
Time Scale
Comparator
Network
Loop Filter
Local Time
Scale
Clock
Recovering
Timing
Signal
Local Clock
Generator
Figure 4. Frequency transport in packet network: through timing packet.
SECOND QUARTER 2020
IEEE CIRCUITS AND SYSTEMS MAGAZINE
11
IEEE Circuits and Systems Magazine - Q2 2020
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