IEEE Circuits and Systems Magazine - Q2 2020 - 22
trace) shows the trend of fi [k] vs. time. Both the offset
error x and random variation re are displayed (ideal rate
is 1, the rate of R[k]).
Figure 12 shows the case of phase-reset algorithm.
In this figure, the trend of logical clock T li [k] is added.
At the very moment of each synchronization, logical
clock's value is simply reset to the value of R[k]. Now,
the synchronization error (the logical clock, the red
trace) is under control as shown in the second graph
from top. However, this algorithm produces problems of
negative-time and time-jump. The 4th graph of figure 12
(the green trace) is the clock movement of logical clock
T li [k] - T li [k - 1] . It becomes negative immediately after
the moment of synchronization. This is caused by the
hard-reset on clock state. In contrast, the movement
of physical clock, the 3rd graph (the brown trace), is
always positive since it represents the advance of real
clock pulses. The effect of random variation, controlled
by re, is also visible.
Clock Time
100
To eliminate the problems of negative-time and timejump, the amortization method is adopted. Instead of a
simple reset, the frequency error induced by x is gradually compensated over a period of 10 intervals (one syntonization period). As a result, the negative-time issue
is nonexistence as shown in the 4th graph of figure 13
(please compare it to the 4th graph of figure 12). And
;T li [k] - R [k] ; is reduced to zero at the end of the 10th
intervals (the brown trace in the 2nd graph).
In previous cases of phase-reset and amortization,
actions are only taken on logical clock. From the 2nd
graphs of both figure 12 and 13, it is seen that the error
on physical clock (the blue traces) grows -unbounded.
The reason is that clock circuit hardware has not been
touched (i.e. the fi [k] is not tuned). To improve synchronization precision, it is desirable to tune fi [k] . This
frequency tuning is accomplished by the procedure introduced in section IV.B, using the TAF-DPS syntonistor.
Figure 14 shows the behavior of physical clock by using
Physical Clock Time T p [k ]
80
60
40
Golden Reference R [k ]
20
0
0
10
20
30
40
50
Real Time
60
70
80
90
100
Clock Time
10
T p [k ] - R [k ]
8
6
4
Error
2
0
0
10
20
30
40
50
Real Time
60
70
80
90
100
70
80
90
100
1.15
Rate
Rate of T p [k ]:fi [k ]
1.1
Offset Error x
1.05
0
10
20
30
40
50
Real Time
60
Figure 11. Time trajectory and synchronization error in a free-run case.
22
IEEE CIRCUITS AND SYSTEMS MAGAZINE
SECOND QUARTER 2020
IEEE Circuits and Systems Magazine - Q2 2020
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