IEEE Circuits and Systems Magazine - Q2 2020 - 24

Clock Time

Clock Time

200.000584249699 MHz. It is off-target by 584 Hz (2.92 ppm)
from its specification. The bottom plot (brown) shows
600  measurements after corrected by TAF-DPS circuit.
Its mean value now is 200.000033609561 MHz. The center
is moved down by 550.6 Hz. After the correction, the offtarget amount is about 34 Hz (reduced from 2.92 ppm to
0.165 ppm). This correction is achieved simply by adjusting some bits in the frequency control word F (please refer to equation (6) and figure 8). This is the experiment
evidence to support the simulation scenarios shown in
figure 14 (the red trace in 3rd graph) and figure 16.
Figure 18 illustrates oscillator's aging scenario and
the corresponding correction by TAF-DPS. To mimic
the aging occurred in real world, a special clock circuit is deigned that produces a frequency-drift-trend
as shown in the blue plot. The aging rate is accelerated
from 0.5  ppb/day (in real world) to 0.5 ppb/minute to
make our test feasible. To counteract this aging, we can
-occasionally (for example, once every few months in
real situation) add a calculated amount to the TAF-DPS's
frequency control F and bring its frequency output back

100

Physical Clock Time: T p [k ]

50
0

to the specified value. The bottom plot (red) shows
the result of this action. As seen, frequency is brought
back to the target every time correction takes place.
Without compensation, the aging-induced drift will
make the frequency off-target by 0.5 ppm after 1000 minutes. With compensation, the drift is controlled within
0.050 ppm all the time.
In following discussion, we will suggest some application scenarios, all related to time synchronization
in one way or another. The purpose is to show that
TAF-DPS based syntonization method is a circuit level
enabler for system level innovation. In first example,
figure 19 depicts a case where a circuit block of "oscillator plus TAF-DPS" functions as a DCXO. This DCXO can
be disciplined by 1 PPS signal (from GPS). The scheme
shown in the left is the traditional approach with a high
price tag since sophisticated circuits and discrete components are used. On the right-hand side, the TAF-DPS
DCXO is a low-cost plan that can be easily integrated
into main processing chip with reasonable area and
power cost.

Reference R [k ]

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Error on Logical Clock: T l [k ] - R [k ]
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Clock Time

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Figure 13. Synchronization behavior using amortization method.
24 	

IEEE CIRCUITS AND SYSTEMS MAGAZINE 		

SECOND QUARTER 2020
IEEE Circuits and Systems Magazine - Q2 2020

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