IEEE Circuits and Systems Magazine - Q2 2020 - 36

obtained by permuting these level hypervectors in this
encoding method. For example, the level hypervector Lr i
corresponding to the i-th feature position is rotationally
permuted by (i - 1) positions, where 1 # i # N. We can
get the final encoded hypervector H by Eq. (16). Such an
encoding process is illustrated in Fig. 7.
H = Lr 1 5 tLr 2 5 g 5 t N - 1 Lr N ,
(16)
Lr i ! {L 1, L 2, f, L m}, where 1 # i # N.

Remark As stated in [29], for speech recognition, the
N-gram-based encoding method achieves lower accuracy
than record-based counterpart. This encoding method is
also used to address data types of letters, such as language
recognition [21] and DNA sequencing [31].
C. Benchmarking Metrics in HD Computing
In HD computing, there is always a tradeoff between accuracy and efficiency, e.g., see [32]. As shown in Fig. 8,
a large amount of work has been carried out to improve
the classification accuracy, energy efficiency, or both at
the same time.

Fmax

Fmin
CiM

CiM

ρN-1

H
Figure 7. N-gram-based encoding [29]. CiM stores level
hypervectors which are mutually orthogonal.

1) Accuracy
In terms of accuracy, the encoding method plays a significant role since each encoding may not be efficient for
different types of data. Good encoding for HD to achieve
high accuracy is hard [33]. In this sense, an appropriate
choice of encoding method can improve the accuracy.
Efficient encoding approaches have been presented in
[34]. The approach in [29] integrates different encoding
methods together to achieve higher accuracy at the expense of hardware area. Compared to single-pass training, retraining iteratively improves the training accuracy [28]. Thus the classification accuracy is improved by
using a more accurately trained model. Moreover, using
binary hypervectors may degrade the accuracy. Hence
with enough resources, non-binary models can be used
to achieve high accuracy.
2) Efficiency
For efficiency, improvements mainly focus on algorithm
and hardware characteristics. From the algorithm perspective, dimension reduction is the most natural way
to realize efficiency. Simulations show that slightly reducing the dimensionality of hypervectors, the classification accuracy still remains in an acceptable range
but saves hardware resources [25]. Binarization, which
refers to employing binary hypervectors instead of nonbinary model, accelerates computation and reduces
hardware resources [35]. The precision is degraded
by quantizing the non-binary HD model. QuantHD has
been proposed in [25] to achieve higher efficiency with
minimal impact on accuracy. Sparsity was introduced in
HD computing in the framework of BSDC [36]. Tradeoff
between dense and sparse binary vectors has been presented in [32]. By introducing the concept of sparsity to
hypervector representation, [37] proposes a novel platform, SparseHD, which reduces inference computations
and leads to high efficiency. From the hardware perspective, HD computing involves a large number of bit-wise
operations, as well as the same computation flow for

HD Computing
Accuracy
Encoding

Retraining

Efficiency
Non-Binary
Binarization

Hardware

Algorithm
Quantization

Sparsity

In-Memory
CNFET

NanoTech
RRAM

FPGA
3D Intergration

Figure 8. Two benchmarking metrics in HD computing and some possible ways to improve these metrics.
36

IEEE CIRCUITS AND SYSTEMS MAGAZINE

SECOND QUARTER 2020

IEEE Circuits and Systems Magazine - Q2 2020

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