IEEE Circuits and Systems Magazine - Q2 2020 - 9

I. Introduction
n architecture planning and engineering construction
of telecom network, computer network or network of
any other types of electronic devices, synchronization
is an important issue [1]. It is the bedrock of the information superhighway. It is the enabler for successful transfer
of voice, data and video over a network. It can optimize
the use of a given bandwidth, increasing throughput in
the case of a fixed spectrum band. Synchronization is also
recognized as the base for Cyber Physical System (CPS)
[2] and Internet of Things (IoT) framework [3]. Moreover,
synchronization is critical in applications of industrial automation and data acquisition, to improve precision, productivity, and quality [4]-[8]. Furthermore, it is crucial to
many other applications [9]-[11].
In past several decades, network architecture has
evolved from the style of synchronous TDM (time
division multiplexing) [12], [13] and architectures of
bus-driven and fieldbus [14] toward asynchronous
packet-based style. The aim is for more efficient use
of spectrum and network hardware [15], [16]. In connected TDM networks, there is physical link for reliable frequency transfer. Therefore, network can coordinate its activities using this common frequency. In
packet-based networks, however, direct physical connection is nonexistent. Both data and timing information have to be conveyed through cell packets. This
presents a different and more difficult challenge for
time synchronization.
In the development of old-time telecom-network
(solely for voice communication) and the newly popular packet-network (mainly for data transfer), there are
three concepts relevant to the transportation of time
signal: frequency transfer, phase transfer and time
transfer. They correspond to three types of systems: frequency-locked system, phase-synchronized system and
time-synchronized system. In frequency-locked system,
all nodes' frequencies remain bounded by a given value.
In phase-synchronized system, the distribution of reference timing signal ensures that their significant events
occur at the same instant (within an accuracy target).
Time-synchronized is similar to phase-synchronized in
that it simply consists of an additional step of naming
the significant instants (e.g. time-of-day information). In
phase- and time-synchronizations, a common notion of
time needs to be established within a network so that
activities in the network can be coordinated. This task
of establishing a common notion of time within a given
network is termed as time synchronization, also commonly
as clock synchronization.

Clock is a physical device that realizes a theoretical
principle: the states of a system repeat at a constant
rate. Time from a clock is defined by counting the states
as they repeat themselves. The transition from TDM network to packet network provokes a suite of new TAACCS
applications that calls for innovation on the design of
clock device used in the communicating nodes [17].
From the aspect of efficient use of timing signal, however, the optimal handling of data in computing and in
networking unfortunately is in the opposite directions.
On one hand, computer hardware, software and networking are all operating in isolated timing processes
(e.g. the layered approach in Open Systems Interconnection model, or OSI model), allowing data to be processed
with maximum efficiency due in part to asynchrony. On
the other hand, coordination of processes, time stamping of events, latency measurement and optimal use of
spectrum are all enabled by timing data which needs
to be accessible by all the involved parties. Thus, the
breakthrough enabling future TAACCS will most likely
come from an interwork of timing and data signals that
break through the existing barriers. One of the solutions
that can positively impact the task of synchronization is
to directly control clock hardware's frequency in higher
layers, not just through the physical layer at the very
bottom as in current practice. This will be a real time
syntonization process (synchronization on frequency)
at hardware level in contrast to the traditional process
of synchronization on time by just adjusting the values
of time registers. This solution demands innovation on
clock hardware since it requires operations much more
than just resetting or adjusting the values of registers.
This new piece of clocking hardware dedicated for performing real time syntonization to assist time synchronization is termed syntonistor.
Time-Average-Frequency Direct Period Synthesis (TAFDPS) is an emerging frequency synthesis technology. It
creates a new type of clock device having salient features
of ample supply of frequency and fast frequency switching (can be loosely viewed as "arbitrary frequency generation" and "instantaneous frequency switching", achieved
simultaneously for a given design) [18]. Its output frequency is precisely predictable with mathematical rigor and is
controlled through a digital word. This type of clocking
device provides us with a means to attack the synchronization problem from a new angle. In this article, TAFDPS is adopted as a tool, called TAF-DPS syntonistor, to
improve the accuracy and precision of time synchronization. We are answering one of the challenges raised in TA- ultidiscipline
ACCS [17]. Meeting this challenge will be a m

Liming Xiu and Xiangye Wei are with BOE Technology Group, Ltd., Beijing, China.
SECOND QUARTER 2020

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IEEE Circuits and Systems Magazine - Q2 2020

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