IEEE Circuits and Systems Magazine - Q3 2020 - 43

It can also be seen from Fig. 11(e) that, above ~1 GHz,
on-board bypass capacitors have lim ite d e f fect.
This is typically re solved by hav ing on- chip bypass capacitors.
VI. Final Notes
A. Skin Effect and Surface Roughness
Current density tends to be higher at the surface of the conductor, especially at high frequencies. The skin depth,
where the current density drops by e -1 from the maximum value, is given by

rfnv

. (6)

drilled vias, where the stub of a through hole via is over
drilled from the back to remove the stub, as shown in
Fig. 13(c). The drawback of back-drilled vias is that the
area beneath each vias is reserved and cannot be used
for routing, which might not be suitable for high-density designs.
Filled-vias are primarily used to enhance the reliability of the PCB. They prevent solder from escaping through the via (solder run-off), which can result
in a disconnection. This is important in packages
such as Ball Grid Array (BGA), where vias might be
beneath the pins. Via filling can be implemented with
epoxy, or with copper to improve electrical and thermal conductivity.

Source

VL2

Load 2

ZL1

Source

VL2
ZL2

VPULSE

VL2

0.5
0

Match

B. Vias
In a multi-layered PCB, a through
holes via can be used to connect
signals between any two layers. In
Fig. 13(a), when the via is used to
connect a signal from the first to
the second layer, it leaves a stub.
Such stubs can disturb the signal
flow as discussed in Section IV-D.
To avoid this issue, blind vias
are used [Fig. 13(b)]. A more cost
effective alternative is using back-

Amplitude (V)

Match

Amplitude (V)

Where μ is the permeability of the conductors ( . n 0 for C. Simulation CAD Tools
copper), and v is the conductance (S/m). From (6), skin Choosing a simulation CAD tool, for testing and veridepth of copper (or gold) is found to be less than 1 μm fication, is typically dictated by a number of paramefor frequencies above 10 GHz, which is smaller than ters. Many of which might not be technical from a PCB
the surface roughness of PCB copper for a typical pro- point of view. Some of these parameters include cost/
cess. As a result, the achieved losses might be higher availability, integration with schematic capture, and
than expected from simulations if the surface roughness is user experience.
not taken into consideration.
Surface roughness are sometimes intentionally added to imLoad 1
prove adhesion between copper
2.5
and substrate material. Some PCB
VL2
2
Source
Load 2
materials with low surface rough1.5
ness, however, are available to
VL2
1
reduce losses from skin effect. For
VL2
ZL1
0.5
comparison, Fig. 12 shows PCB
traces with ideal copper surface
0
Source
VL2
0
5
10
15
(no roughness) and with realistic
Time (ns)
surface roughness.
ZL2
Losses attributed to surface roughVPULSE
ness might be hard to distinguish
(a)
from the ones due to the dielecLoad
1
tric substrate. In [32], a method is
2
presented to separate the two loss
mechanisms in situ.
1.5

10
Time (ns)

(b)
Figure 10. (a) In the presence of a stub in a signal path, reflections can disturb the
signal quality. (b) Re-routing the path such that stubs are eliminated can eliminate
the disturbance. TLs are 2 ns long in this simulation. LTspice is used to model and
simulations.

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IEEE CIRCUITS AND SYSTEMS MAGAZINE

IEEE Circuits and Systems Magazine - Q3 2020

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