IEEE Circuits and Systems Magazine - Q3 2020 - 44

Generally speaking, post-layout simulations can be
done in circuit level (SPICE, e.g. [33]), or electromagnetic level (FEM, e.g. [34], [35]). The latter is more common
for PCBs since it produces more accurate results, at the
cost of being more computationally-intensive. Circuit
level simulations require careful modeling of each trace

as a transmission line, along with their proper respective couplings.
Comparing the performance of simulation softwares
is not easy. For any CAD tool, accurate modeling of the
substrate material, metal conductivity, and surface roughness, for instance, will result in fewer chances for errors.

102
C

L1

L2

L3

L4

L5

R1

R2

R3

R4

ZCAP (Ω)

1
R5

R6

1n
10

101

0.1

100

F

nF

ESL ESR

C

1

2

µF

1µ

F

10-1

2
10-2
105

(a)
ZV DD

1 µF

0.1 µF

10 nF

101

Load
ZV DD (Ω)

l = 25 mm l = 3.5 mm l = 3.5 mm

VIN

(c)
l = 3.5 mm

VIN

ZV DD

10 nF

106

107
108
Frequency (Hz)
(b)

TL Width = 0.2 mm

109

1010

TL Width = 1.1 mm
TL Width = 4 mm

100

10-1

Load

10-2
105

Power Plane and
TL Width = 1.1 mm
106

(d)

107
108
Frequency (Hz)
(e)

109

Transmission S21 (dB)

Figure 11. (a) A model of a real capacitor (based on C0603 series from TDK). (b) The impedance of a capacitor versus frequency
for a simplified model, containing only ESR and ESL. After the self resonant frequency, the capacitor behaves like an inductor, and
cannot be used to suppress ripples on supply rails. ESR determines the depth of the notch, and ESL dictates the self resonant
frequency. (c) The supply rail is connected to the load using a microstrip. Large bypass capacitors are placed further from the load,
while small ones are placed closer. (d) Power planes provide low impedance on the supply rails, especially at low frequencies.
This results in a smaller number of required capacitors. (e) Simulated results from microstrip lines setup in (c) and the power
plane setup in (d). Wide microstrip lines give lower impedance at the supply rail. Power planes, however, give the best results.
(Simulations are based on: RO-4350B, 20-mil substrate, using LTspice.)

Top Layer

0
Smooth Surface

Stub

-1

Bottom Layer

Rough Surface
-2
-3

(a)

60 mm
1

Inner Layer
2

5

10
15
20
Frequency (GHz)

Inner Layer

Blind Via
25

(b)

30

Figure 12. Transmission of a microstrip line with and without
surface roughness. Surface roughness adds additional
losses especially at higher frequencies. (Simulations are
based on: RO-4350B, 20-mil substrate, using ADS).

44 	

Inner Layer

Back Drill
(c)

Figure 13. (a) Through hole vias can leave undesirable
stubs in multi-layer PCBs. (b) Blind vias eliminate the stubs,
without affecting routing on other layers. (c) Back-drilled vias
also eliminate stubs at a lower cost, but routing on other
layers is blocked.

IEEE CIRCUITS AND SYSTEMS MAGAZINE 		

THIRD QUARTER 2020
IEEE Circuits and Systems Magazine - Q3 2020

Table of Contents for the Digital Edition of IEEE Circuits and Systems Magazine - Q3 2020
