10 Rec. Channels VLED ChR2 Mouse/Rat ADC/HP/LP Detection Compression Ref (a) Closed-Loop Decision Closed-Loop Stimulation CL Controller Monitor the Detected AP Clusters Control-State Machine CLK Generator PWM Current Reference SPI Master (x5) CLK NonOverlapping Clock First Order ââ First Order ââ First Order ââ Active Neuron Counter in Time Window (b) LDO 3/4 VDD Digital Pre-Subtraction Digital Pre-Subtraction Wide-Swing Current Mirrors Stimulation PWM Generator Igloo FPGA Wide-Swing LED Channel With Feedback Opt. Stimulation Sorting Control Logic (d) Z -1 Z -1 2 3 SPI Module 2 2 Z -1 Z -1 + + - + - + Ch Sel. 3 2 2 2 1 AP 3 1 3 3 3 3 1 Neuron 3 is Active 4x in Window => Light Pulses (Configurable for Each Clusters) 1 3 Clusters No. Sliding Time Window ... COMB Stages M Integrators Stages Decimation Filter Circuits Duplicated 10x SPI Communication Buses Logic Control Module Z -1 Z -1 + Reconstruction Clock Divider 1 1 1 Circuits Duplicated 10x ââMASH 1-1-1 ADC Digital Pre-Subtraction Modules 1/4 VDD 3-Bits BW Selection Pseudo Resistor Bank Gm-C Filter Programmable Band-Pass Filter Optical Stimulation Circuitry - + Low-Noise Amplifier 0.13 µm SoC SRAM Windowing (~3 ms) AP Alignment AP Detection Dynamic Requantization Symmlet-2 Lifting DWT Control + SPI Min Distance to Clusters Cluster Assignation (c) SRAM Cluster Merge and Update Minimal Distance Between Clusters Classification Control + SPI Dynamic Normalization Sorting Tree Retained Coefficient Selection Compression Control + SPI Offset Removal (IIR) STD Estimation Threshold Computation AP Detection 0.13-µm Neural DSP Figure 3. System-level concept of the wireless CL optogenetic headstage using the proposed mixed-signal chip and neural DSP as core modules: (a) The headstage is connected to the optrode and mounted on the head of the animal, (b) a custom 0.13-µm CMOS mixed-signal chip is used to perform neural recording and optogenetic stimulation in parallel, (c) the 0.13-µm CMOS Neural DSP has 3 cores for AP detection, compression and classification and (d) the CL algorithm is performed within a low-power FPGA. 4 Stim. Channels (LEDs) ... Implantable Module >> FOURTH QUARTER 2020 IEEE CIRCUITS AND SYSTEMS MAGAZINE 33