IEEE Circuits and Systems Magazine - Q4 2020 - 34

Scaling down the embedded electronics by using custom integrated
optical stimulation and low-noise data acquisition circuits allows
to look at much more neurons in parallel.
chip and the Neural DSP module, the headstage encompasses two other building blocks: i) an ultra low power
Igloo AGLN250 FPGA (5 Ã 5 mm2 ÂµBGA) controller from
Microsemi, USA, and ii) a low-power nRF24L01p wireless
transceiver from Nordic Semiconductor, Norway.
As shown in Fig. 3(d), the FPGA controller is used
for interfacing with the proposed Neural DSP chip, the
mixed-signal chip and the wireless transceiver using
dedicated master SPI modules. The use of an FPGA provides all the necessary flexibility to ease system integration. An Igloo FPGA was selected for its low-power consumption and its small footprint. Within the FPGA, the
neural data is routed from the mixed-signal chip readout
to the Neural DSP detector core. Then the detected APs
are forwarded to the Neural DSP compression core, and
finally a subset of the compressed waveforms are routed
to the Neural DSP classification core. When ready, the
sorting number and AP detection timestamp are routed
to the CL algorithm circuit within the FPGA. When a CL
stimulation pulse is triggered by the CL algorithm circuit, the FPGA controls the light pulse stimulation sequence through a feedback scheme established with the
mixed-signal chip stimulator [17]. With this system, the
latency measured as the duration between the end of
the acquisition of the last AP sample and the activation
of a CL stimulation pulse can be less than 1 ms [15].
IV. Mixed-Signal Neural Front-End IC
Each multimodal neural recording channel includes a
low-noise bio-amplifier with programmable bandwidth
(BW), a DR MASH 1-1-1 ADC with programmable resolution followed by a decimation filter (DF). On the same
die, optical stimulation is performed by a 4-ch LED driver circuit with feedback that precisely sets the effective
forward current of each LED. Each building block of the
mixed-signal chip is reviewed in this section.
A. Bio-Amplifier Design
Fig. 4(a) shows the schematic of the single-stage fullydifferential AC-coupled bio-amplifier utilized in the
mixed-signal chip, inspired by [40]. In this design, the
ratio of capacitor C 1 /C 2 sets the mid-band gain Am, and
the high-pass cutoff frequency is determined by the resistor R and the capacitor C2, so FHP = 1/ (2rRC 2). The
feedback resistors R use a 3-bit tunable pseudo-resistor
bank, allowing the selection of a given high-pass BW for
collecting either LFP and/or AP signals. The feedback
34â

pseudo-resistor bank of Fig. 4(a) consists of PMOS pseudo-resistors whose gates are connected in a back-to-back
configuration through CMOS transmission gates. These
pseudo-resistors allow for equivalent resistances in the
Tera-Ohm range, which is required to implement very-low
high-pass cutoff frequencies down to a few mHz for LFP
recording. The switches S 1 - 3 within the pseudo-resistor
bank are transmission gate structures implemented with
thick oxide transistors of smallest width providing small
subthreshold leakage current, high threshold voltage,
and low oxide capacitance per unit of area compared
with equally sized transistors of standard thickness.
The low-pass analog cutoff frequency is set by the
loading capacitance CL and the transconductance Gm of
the operational transconductance amplifier (OTA), i.e.,
FLP = G m / (2rA m C L). The OTA, the schematic of which is
shown in Fig. 4(b), consists of a fully differential foldedcascode amplifier with source-degeneration resistors
to reduce thermal noise [41]. A source-degeneration resistor topology effectively reduces the IRN, while being
simple to implement and needing only small overhead.
The input-referred noise (IRN) is expressed by:

8kT g + 2 + 4 g , (1)
2
V ni
m
, OTA =
2 c m3
R 1, 2 3 m5
gm
3

where k is the Boltzmann constant, T is the temperature
in Kelvins, and g m3 and g m5 are the transconductance
of transistors M3 and M5, respectively, in Fig. 4(b). The
flicker and the thermal noise contribution of M11 and M12
are minimized through the use of source degeneration
resistor R 1, 2 , as long as the condition g m11, 12 Â·R 1, 2 & 1 is
met [41]. Thus, if R 1, 2 is big enough, the noise contribution of the resistor to the output noise is better than the
transistor pair M11 and M12.
B. DR MASH 1-1-1 Neural ADC
Typically, the bio-amplifier IRN, the total harmonic distortion (THD) and the unpredictable background neuronal noise put a limit on the maximum achievable resolution of the whole system. For instance, the thermal noise
floor can be as high as 10 ÂµV p - p , or above, for AP recordings with metal electrodes [18], [20], leading to a maximum effective number of bits (ENOB) of 9 bits assuming an input dynamic range of 6 mV p - p . Previous work
targeting both APs and/or LFP reported resolutions of
8-bits [42] and 10-bits [43], [44]. Thereby, we designed
a DR MASH 1-1-1 neural ADC topology that meets the

IEEE CIRCUITS AND SYSTEMS MAGAZINE

FOURTH QUARTER 2020

IEEE Circuits and Systems Magazine - Q4 2020

Table of Contents for the Digital Edition of IEEE Circuits and Systems Magazine - Q4 2020