R C2 + A1 - Z -1 Z -1 Z -1 Z -1 Ï2 C2 Ï1 C2 Ï1 SC Offset Cancelation Ï2 Ch1 Ch2-10 Z -1 Z -1 + - + + + DAC1- (a) A - C3 - + DAC1+ Signal - + Centering + + - Bias_enable C3 To ââMASH 1-1-1 Gain = C1/C2 = 25 pF/ 125 fF = 200 V/V C1 C1 - '1' - + + Ï1 + Latch1 Fs Z -1 26 bits Ï1 D Latch + Fs Z -1 26 bits -DACref +DACref Thick Oxide Latch1 S3 + Ï2 Ï2 V- (d) Fs Z -1 25 bits (c) Stage 3 Stage 2 Ï1 - l1 + Ï1 Pesudo-Resistor Bank Adjustable for LFP, AP or for Both, FHP = 1/(2ÏRC2) (0.5-400 Hz) S1 S2 + Ï2 C2 C2 Ï2 Z -1 Fs/M Ï1 Ï1 Vb4 A DAC2+ + - C3 Fs/M Z -1 + 19 bits - (b) R2 M12 M10 M8 Vo - M6 M13 C3 Vb7 Vb6 M20 M19 + Fs/M Z -1 18 bits + To Stage 3 +- - - Fs/M Z -1 17 bits + - Vb7 Vb6 Vref2 Vcm M22 M21 M14 Fs/M Z -1 16 bits + - C4 Vref1 Vcm S3 S2 S1 Vref2 Vref1 Channel Selection Latch1 To Stage 3 Positive Node Ï1 D Latch Vcmfb Vcm Latch1 -I1(z))·(1/(z-1)) + EQ2(z) Latch2 Ï1 Latch2(z ) = (DAC1(z)-DAC2(z ) DAC With Pre-Subtraction Module Vcmfb Vb5 C5 Vb3 Bias_enable C3 R1 DAC2- M11 M9 Vo+ M7 M5 Clock Reduction Factor V+ SC Offset Cancelation M4 M2 M1 21 bits Fs Vcm C1 C1 Ï1 Vcm M3 Vb2 Vb1 M15 Latch3 Vo+ Figure 4. (a) Schematic of the bio-amplifier design with programmable high-pass cutoff frequency. The feedback resistor uses a 3-bit pseudo-resistor bank. (b) Circuit schematic of the OTA used for the bio-amplifier and its continuous time CMFB. The fully-differential folded-cascode OTA with source-degeneration resistors R1 and R2 is used. (c) Schematic of the DR MASH 1-1-1 using a digital pre-subtraction module for the 2nd and 3rd stages. (d) CIC4 decimation filter with optimized binary precision between the stages, for up to 14-bit output resolution. The low-pass cut-off frequency can be programmed simply by changing the clock reduction factor M and/or by modifying the oversampling frequency. Ch 1 Ch 2-10 Ï1 Ï1 Vcm C1 Ï1 Ï2 C1 Ï1 Ï2 Vcm Light Beam Stage 1 + X - Cells Ref Electrode Recording Electrode >> 3-bit Signal From ââMASH 1-1-1 M16 C2 >> R Ï1 M17 S2 S2 S1 S3 M18 S3 S1 + Optical Fiber To Control Module + - FOURTH QUARTER 2020 IEEE CIRCUITS AND SYSTEMS MAGAZINE 35