IEEE Circuits and Systems Magazine - Q4 2020 - 36

required resolution for this application (~10 bits [43],
[44]) with a low oversampling ratio (OSR) (#25). Specifically, using an oversampling ADC in this application provides the following key advantages: 1) the flexibility to adjust the ENOB and the power consumption
with respect to the requirements and the variability of
the application (type of target signals to collect, noise
level and type of electrodes (e.g. glass micropipette,
metal or silicon electrodes, etc.), or SNR degradation
reported in chronically implanted electrodes [45], 2)
a programmable low-pass cutoff frequency, performed
implicitly by the DF, 3) the relaxation of the bio-amplifier anti-aliasing filter constraints by pushing the
Nyquist's frequency away from the in-band signal
through oversampling, 4) the stability and robustness
at full-scale, thanks to the 1st order DRs in the MASH,
an important requirement in biomedical applications
in general, and 5) the opportunity to use low OSR for
enabling low-power, easy interfacing, and the utilization of an on-chip DF, thanks to the 3rd order noise
shaping characteristic.
The circuit schematic of the DR MASH 1-1-1 neural
ADC is shown in Fig. 4(c). Each DR stage in the proposed
MASH 1-1-1 topology requires an OTA for the integrator,
a one-bit quantizer, a DAC for the 1st stage and a presubtraction module for the 2nd and 3rd stages. More details about the implementation of each building blocks
can be found in [17].
C. Filtering & Decimation
Fig. 4(d) shows the block diagram of the 4th order cascaded integrator-comb (CIC4) DF utilized in this design.
In contrast to [34] and [46], using an on-chip DF provides
programmable precision and adjustable bandwidth simply by varying the OSR and the clock reduction factor
M (see Fig. 4(d)) depending on the bio-amplifier performance and type of signal (i.e., LFP or AP). This filter
uses a highly optimized CMOS implementation strictly
based on adders and registers, avoiding power-hungry
multipliers and dividers. For using as few output bits per
stage as possible without degrading the precision, the
minimal binary precision of each stage is determined
using the Hogenauer pruning technique, to accommodate OSR # 50. Since the DF has a rather smooth cutoff
frequency, it is designed to provide an attenuation of
15 dB at the Nyquist frequency (F NF ) after decimation,
by setting M equal to the OSR value. The transfer function of the DF is:
	

H (z) = A PR Â· (1 - z -M ) 4 / (1 - z -1) 4, (2)

where M is the clock reduction factor between the integrator and comb stages, and APR is the gain reduction induced
36â	

7

by pruning. This gain is defined as A PR = 1/2 (Rk = 0 B p,k) - 1,
where B p, k is the number of bits pruned at stage k,
thereby R 7k = 0 B p, k = 10. The time-domain low-pass cutoff
frequency relates to the OSR by: FNF = Fs /2Â·OSR. Thus,
the advantage of using an on-chip DF is clear, since it
allows the implementation of a programmable low-pass
filter simply by changing FS , the OSR or the M factor.
D. LED Driver Circuit Design
The LED driver is a crucial element in an optogenetic
system because it determines the amount of optical
power delivered to the neurons. We developed a 4-ch
LED driver that precisely regulates the LED current and
that is robust against the LED parameter and the battery voltage variations. The LED current is modulated
by an external PWM signal, and each channel can be
independently turned ON or OFF, by sending the LED
configuration bits using a custom serial digital input.
The circuit schematic of the 4-ch LED driver is presented in Fig. 5. Compared to previous designs [47],
[44], [48] and [49], this circuit allows to precisely control the value of the forward current into each LED using a regulated cascode current source with feedback.
The current can be adjusted independently of the LED
parameters (forward voltage, etc.) and the battery
voltage, guaranteeing that the right optical power is
delivered by each LED into the implanted fibers to
properly activate the ChR2 neurons [22] (>0.1 mW/mm2
at the tip). Each channel can be activated by writing a
4-bit word in the shift register using the LED control
and CLK signals. The driving current is modulated by
an external PWM signal. It is worth noting that the key
of this topology is the wide swing current mirror in the
LED current path that keeps the drain-source voltage
of M2 at the edge of saturation (Vds2 . Veff ), while M1
can enter the triode region without significantly impacting the drain current, which both minimizes the
voltage drop inside the chip to accommodate smaller
battery voltages. The efficiency of one channel of the
LED driver is of 87% (w/the current reference, I LED =
20 mA, VLED, anode = 3.7 V) [17].
V. Digital Neural Signal Processor IC
This IC includes three main cores:
1)	 The Detector core detects and extracts the AP of
individual neurons. It uses an adaptive threshold based on real-time signal analysis performed
through a feedback loop, which uses an efficient/
optimized implementation [20].
2)	 The Compression core uses a Symmlet-2 (Sym-2)
discrete wavelet transform (DWT) lifting scheme
followed by dynamic coefficient discrimination
using a sorting tree and dynamic coefficient

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