IEEE Circuits and Systems Magazine - Q4 2020 - 37

The digital neural decoder IC detects, compresses, and sorts the action potential
waveforms on-the-fly without supervision, on all the recording channels in parallel.
This information can then be used to apply complex closed-loop schemes.

From External Controller

A. AP Detector Core
The proposed detector core has two main modules:
the pre-processor for conditioning the neural data
and the adaptive threshold for discriminating the
APs from noise.

Control Logic
D1

LED Control

D FilpFlop D1

D2
D FilpFlop D2

1) Pre-Processor
The proposed pre-processor is based on the absolute
value operator [50]. As previously demonstrated, this
simplified operator can be as efficient as a more sophisticated energy-based operator, such as the non-linear
energy operator (NEO), the smoothed NEO and the
matched-filter (MF), providing an excellent trade-off between low complexity and high performance [50], [51].
The absolute value operator concept is shown in Fig. 6.
Upon threshold crossing, the APs are extracted and
aligned on their peak amplitude sample.
Fig. 7(a) shows the detector core diagram. First, the
neural signal is high-pass filtered by an infinite impulse
response (IIR) notch filter to remove any DC level. Upon
signal threshold crossing, the peak sample is found
across a 31-sample window immediately starting after
the detection point. Then, a frame of 48 samples including the peak at the middle is forwarded to the compression core. Such an alignment around the peak value is
used to facilitate AP classification, given that two APs

D3
D FilpFlop D3

D FilpFlop D4

CLK

PWM

Current
PWM Reference

Vbias2

M11

R1
External

Vbias1

M10

R1 and R2 Are
External Resistors
for Current Tuning

Iref Ã 2

+
A1

Iref Is Generated
Only When PWM
Is High

Battery, ex:
LiPo 3.7 V

ILED =
200 Ã Iref

Current Boosting/Sensing

D1 && PWM

M12
Iref

External

D4
Control Signals

r- e-quantization scheme for neural data compression [20]. Each AP waveform is compressed for
saving power and bandwidth, and transmitted
wirelessly along with the classification ID for live
monitoring. Additionally, the data compression
allows to operate the wireless transceiver in lowdata rate mode, which extends the lifespan and
increases the transmitting range.
3) The Sorting core sorts the AP on-the-fly according to their wave shapes. For performing efficient
classification this core reuses a subset of the DWT
coefficients from the compression core.
Each building block of the Neural DSP IC are detailed
in the following sections.

D1 || PWM
Current Feedback

M2
Ch 1

Wide Swing Current Mirrors

Ch 2..4
Large W/L = 1,500 for Good Matching
Between the Channels

Figure 5. Circuit schematic of the 4-ch LED driver. This circuit allows us to precisely control the value of the forward current in
each LED using a regulated wide-swing current source with feedback. The average driving current is modulated by an external
PWM signal.
FOURTH QUARTER 2020

IEEE CIRCUITS AND SYSTEMS MAGAZINE

IEEE Circuits and Systems Magazine - Q4 2020

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