IEEE Circuits and Systems Magazine - Q4 2020 - 38

emitted from the same neuron might appear to belong to
different clusters if they were misaligned and not properly extracted.

vided in Fig. 7(b)(top)), are stored inside general-purpose
constant registers within the computation unit.
2) Coefficient Sorting Stage
The proposed system uses a new sorting tree circuit to
find the coefficient having the Nth amplitude (CN). As
shown in Fig. 7(b)(middle), the proposed sorting tree circuit has 48 nodes, each of which encompasses different
memory space, including a DWT coefficient, the number
of greater coefficients, and two memory pointers. The
left and right memory pointers each link to the next
node with a smaller or greater coefficient amplitude,
compared to the current node coefficient. The tree is
gradually filled, as the coefficients are produced by the
lifting circuit. More details about the tree's functioning
are provided in [15].

2) Adaptive Threshold
The output of the absolute value operator is compared with a threshold, the value of which is recalculated in real time according to the characteristics of
the neural signal. The proposed threshold calculation
strategy is based on the estimated standard deviation
( v a ) of the noise embedded in the neural signal. This
strategy is effective and robust, and is used extensively in electrophysiology [52], [53]. The detector core
computes v a through a feedback loop that is using
the statistical property of the signal's noise [20], [52],
as seen in Fig. 7(a).

3) Compression Stage
During the compression stage, the coefficients greater
or equal to C N are retained, normalized, and quantized
from 16 to 6 bits, while the other coefficients are discarded [20], as shown in Fig. 7(b)(bottom). The position
of the retained coefficients are stored inside a 48-bits array. A coefficient normalization is performed by dividing
the retained coefficients by Cmax, while a requantization
is performed by keeping the 6 MSB of the division. Only
Cmax is kept on 16 bits for allowing a resolution equivalent to the original neural data in the AP reconstruction.

B. AP Compression Core
The detected APs are forwarded to the compression
core, which can increase the number of recording
channels, reduce power consumption, and increase
the transceiver range, while providing a dimensionality reduction to help the sorting core. As shown in
Fig. 7(b), the DWT-based compression technique uses
three pipelined stages. First, a 4-Level Sym-2 lifting DWT
is applied, followed by a coefficient sorting stage, and
finally by a compression stage.
1) Symmlet-2 Lifting DWT Stage
In the first stage, a Sym-2 lifting DWT is performed on each
of the detected AP waveforms. The Sym-2 lifting scheme
diagram is shown in Fig. 7(b)(top), and is performed sequentially using a FIFO, a finite stage machine (FSM) and
a computation unit. When a new AP becomes available
inside the FIFO, the FSM begins the lifting sequence. The
filter coefficients and scaling factors H1-H5, (values pro-

Voltage

Neural Signal

C. AP Sorting Core
A major burden for AP sorting is the dimensionality reduction step, which consumes time, power, and area
[12], [18]. Fortunately, the aforementioned compression
core produces a dimensionality reduction at each of the
DWT levels. The proposed strategy consists of generating a 6 Ã 6-bit element vector per AP using the level-3

|Neural Signal|

Detected AP Window

AP Centering

Detection Points

Threshold

Centered Around the
AP Max Amplitude

Rat Neural
Signal [x, x]

Time

Figure 6. The pre-processor concept, when the amplitude of the neuronal signal exceeds a threshold, retrieves a detected AP
waveform window set around the peak amplitude.
38â

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IEEE Circuits and Systems Magazine - Q4 2020

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