IEEE Circuits and Systems Magazine - Q4 2020 - 39

FOURTH QUARTER 2020 		

IEEE CIRCUITS AND SYSTEMS MAGAZINE	

39

IIR

|x|

Ch Number: 1..10



Wait for Vector

Load Cluster
Means Vectors
From SRAM

6 Ã 6-Bits Vector

Dimensionality
Reduction

Spike (48 Samples)

Calc. Min
Distance (L1)
to Clusters

X

+

+

Moving
Average

(c)

Update
Cluster
Average

Assign to
Existing
Cluster

No

Yes

Dmin1 > T1?

-

>

Yes

AP?

Cluster Number

Cluster Found

Centered AP

Output 47
Samples
Around Max
Amplitude
Sample

Calc. Min
Distance (L1)
Between Clusters

Null

Null

+

Right cnt.

Smallest Coef to Retain Amplitude
Threshold (Cthr, at Step 2)

Level 4 Level 3
Level 2
Level 1
DWT Coefficient Amplitude

Split

+

Recursive

H1
H2
+

H3

Z -1

Leaf and Coef <
Current Node Coef?

Left cnt.

(b)

Right cnt.

Coef Value

H5 = (â(3)-1)/â(2)

H2 = â(3)/4
H3 = (â(3)-2)/4
H4 = (â(3)+1/â(2)

H1 = â(3)

To Level 3

48

2

1

6b

6b

6b

Left cnt.

6b

6b

6b

Right
cnt.

6b

6b

6b

Next
Addr.
Right

6b

6b

6b

16 b

16 b

16 b

Coef.

Maximum
Coef Found
(Cmax)

Next
Addr.
Left

No
Nodes Memory (240 Bytes)

Load Next Node

Yes

Coef Amplitude = Max Coef
Amplitude?

Load Next Node

Yes
Smallest Coef
to Retain
No
found (Cthr)

-1

0

111111101111100001100001000000000011110000000001
Compressed Coefs

Retained Coefs Array

6-Bits Normalized Coefs (Used for Compression and Clustering)
1
CR = (48 Coefs. Ã 16-Bits)/
(48-Bits + 16-Bits + N Ã 6-Bits)

Next addr. Next addr.
Right
Left

6-Bits
Requantization
For Each
Retained Coef

0
Null
Next Tree Node Right

Compressed Coef
= Coef/(Max Coef)

Increment Right cnt.

0
Null

New Coef

H6

H5

Right cnt. = Nb coefs to keep minus one (N-1)?

H4

+

Compression Core

New Tree
Update Next Right Addr. Node Right

Update Right cnt.

Current Tree Node

No Yes, Load Node at
'Next addr. Right' and

No

Yes

Coef > Current Node Coef?

Increment Left cnt.

No, Load Node at 'Next
addr. Left' and

Yes

Leaf and Coef >
Current Node
Coef?

Next addr. Next addr.
Right
Left

Left cnt.

H6

H5

Yes, Load First Node

H4

+

Coef Value

No

FIFO

Q2

Z -1
Q0
H3

Maximum Coef Amplitude (Cmax, at Step 2)

Stage 3 (Compression)

Next addr. Next addr.
Right
Left

Right cnt.

Coef Value

Next Tree Node Left

0

H2

Q1

Last Coef?

H1

+

Update Next Left Addr.

0

Left cnt.

Xo(n)

Update Right cnt.

New Coef

New Tree
Node Left

Xe(n)
Split

Recursive

Stage 2 (Tree Sorting)

Spike
Samples

Stage 1
(4-Level DWT)

L3 of the DWT Compressed APs

Dmin2 <
T2?

Yes

Update
Cluster
Average

Write
Merged Cluster
to SRAM

No

Max Amplitude

AP Extraction

Wait for
Maximum
Amplitude
Sample in
Window

Write New
Cluster to
SRAM

Neural
Signal

(a)

Threshold

Feedback

Ïa

Target
(31.7%)

Error (E)

Integrator

Pre-Processor

Detected and Centered APs

Figure 7. Bloc diagram of the digital neural signal processor IC: (a) The detector core diagram, (b) the AP compression core circuit consists of three pipelined stages: a 4-Level
Sym-2 lifting sequential DWT is performed on each detected AP (top), the detailed coefficients are processed by a sorting tree to find the coefficient having the Nth and the maximum amplitude (middle), and compression occurs by dynamically thresholding the DWT coefficients to keep only N of them. Further compression is provided using a dynamic requantization operation (bottom), and (c) the classification core, which is using an unsupervised algorithm. The classification core circuit can handle up to five clusters per channel
and reuse the VL3 vector produced by the compression core and the va found by the AP detector core.

Thr2

Thr1

+

Gain (Gthr)

Sorting Core

Adaptive
Threshold

+

Noise Shaping
Filter

...

...

PWM

+

Comparator
(>)

Quantization
Noise

Process (G(z))

Digitized Neural Signal (Ch. 1-10)

Detector Core
IEEE Circuits and Systems Magazine - Q4 2020

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