IEEE Circuits and Systems Magazine - Q4 2020 - 41

predetermined amount of occurrences is found within
a sliding time window. The duration of the sliding window can be configured to target numerous types of recognizable firing patterns, such as AP bursts of varying
lengths, while the stimulation patterns, i.e. number of
pulses, pulse width, and the stimulation channel, are
also configurable.
A CL scheme is illustrated in Fig. 8. It is optimized
to use only basic FIFO structures implemented inside
the low-power FPGA. The CL circuit works as follow:
Each cluster pertaining to each channel is associated
with a unique FIFO in SRAM memory, which contains
the latest AP timestamps for that cluster. When a new
AP-to-cluster association becomes available, a memory pointer to the FIFO structure belonging to that
cluster is retrieved. If the FIFO is empty, the AP timestamp (TNEW ) gets enqueued. Otherwise, the module
reads the older timestamp (TOLD) at the top of the
FIFO. If TOLD - TNEW is greater than the sliding window
length, the top of the FIFO is dequeued. Then, TNEW is
enqueued, and if the FIFO size is equal to the number

of APs required to trigger a feedback stimulation pattern, the FIFO is cleared and a trigger is issued.
VII. System Integration and Encapsulation
The mixed-signal chip and the Neural DSP chip are then
grouped together onto a lightweight printed circuit board,
and encapsulated to form a miniature headstage, which
can be implanted inside the brain of a freely behaving rodent. The micrographs of the mixed-signal and the Neural
DSP chips are shown in Fig. 9(a). The mixed-signal and
Neural DSP chips are directly wirebonded on the headstage PCB to save space, next to the low-power FPGA. The
headstage consists of two interconnected PCBs: i) the
base PCB where the ICs are wirebonded, and ii) the PCB
that holds the wireless transceiver placed at 90 degrees
from the first PCB. The fully encapsulated headstage is
shown in Fig. 9(b). A drop of epoxy is applied on the dies
to protect the wirebonds, and a 40-mAh LiPo battery is
placed above the electronic components to fill any unused space. The packaged system with the battery
weighs only 3.0 g and occupies as little space as 1.13 cm3.

Packaged Weight With Battery: 3 g
Wireless Transceiver2

CL FPGA1
Controller

1.16 cm

1 mm

Mixed-Signal Neural Front-End IC [16, 18]

On-Off Switch

1.61 cm
Digital Neural Signal Processor IC [18]

2 mm
Classification SRAM

1 mm

Threshold SRAM
AP Detection Core,
Compression Core
and Classification Core
(ARM Logic Cells)

40 mAh Battery

AP Detector SRAM
Detected AP FIFO SRAM

1 cm

1.2 mm
1AGLN250V2
2nRF24L01+

(Microsemi)
(Nordic Semiconductor)
(a)

(b)

Figure 9. (a) Chip micrograph, printed circuit board floorplan and wireless headstage w/Neural DSP for CL optogenetics (1.05 g).
(b) Different views of the packaged headstage w/the battery (3.0 g), a typical optrode is also shown.

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IEEE CIRCUITS AND SYSTEMS MAGAZINE

IEEE Circuits and Systems Magazine - Q4 2020

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