IEEE Circuits and Systems Magazine - Q4 2020 - 61

2007
150 nm GaAs
Conventional Doherty PA
19-21.8
5
7
25 @ 42 GHz
>17
38-46

Output collector efficiency.
b
At saturation.
c
Small signal.

[62]

a

2019

c

2016
45 nm SOI CMOS

100 nm GaN
Conventional Doherty PA

Transformer based Doherty PA
20.1

32
12

2
13

13
30

26

27.5-28.5
[61]

28

60
[60]

16.6

2019
130 nm SiGe BiCMOS
Transformer based Doherty PA
16.8/17.1/17
1.5
18.2/17.1/16.6
20.3/22.621.4
28/37/39
[59]

13.9/16.6/12.6

2018
130 nm SiGe BiCMOS
Post-matching Doherty PA-Dualfrequency architecture
23.7 @ 40 GHz
4
>20
30-55
[58]

>16a

23.4 @ 40 GHzb

2013

2015
40 nm CMOS

45 nm SOI CMOS
Conventional Doherty PA- Active
phase shift

Transformer based Doherty PA
21

18
2.5 & 1.2

1.2
18.3

8
20

13.6

42
[57]

21

60-81
[56]

7

2017

Year
Process Technology

65 nm CMOS
Conventional Doherty PAAdaptive biasing network

Design Technology
Pout (dBm)

>11.8
1.6
-
>17
57-64
[55]

>8

Voltage
Supply (V)
Gain @
6 dB (dB)
PAE. @ Sat.
(%)
PAE. @ 6dB
OBO (%)
Freq.
(GHz)
Ref

Table III.
The comparison with state-of-the-art wideband mm-wave Doherty PAs.

FOURTH QUARTER 2020 		

that reduced the impedance transformation ratio at
back-off. This improved the bandwidth and powercombining efficiency. A " driver-PA co-design " method that creates power-dependent uneven feeding in
the Doherty PA and enhances its operation without
any additional hardware or compromises in bandwidth was also devised. For the proof of concept,
a 28-/37-/39-GHz Doherty PA was implemented in a
standard 130-nm SiGe BiCMOS process, which occupied 1.8 mm2. The Doherty PA achieved a 52%
â3 dB small-signal S21 bandwidth and a 40% â1 dB
large-signal Psat bandwidth. At 28/37/39 GHz, the
PA achieved +16.8/+17.1/+17 dBm Psat, +15.2/+15.5/+
15.4 dBm P1dB, and superior 1.72/1.92/1.62 times efficiency enhancement over class-B operation at 5.9-/6/6.7-dB OBO.
Designing Doherty PAs at the higher millimeterwave (mm-Wave) range remains a major challenge
because most Doherty combiners at these frequencies are not efficient. To resolve this bottleneck,
the balun response was analyzed under load variation and subsequently proposed for the Doherty
PA architecture with impedance inverting and scaling baluns. This performed active load modulation
on differential PAs and delivers combined power to
a single-ended load in [60]. Using a 45-nm Global
Foundries CMOS SOI process, a Doherty PA was fabricated, and demonstrated 20.1 dBm Psat, 19.3 dBm
P1dB, 26% peak PAE, and 16.6% PAE at 7-dB back-off
point from OP1 dB at 60 GHz.
In [61], a Doherty PA realized using a 100 nm gate
length Gallium Nitride on Silicon (GaN-Si) technology for 28 GHz 5G applications was presented. The
Doherty PA was based on a two-stage symmetric architecture, resulting in a 3 Ã 2 mm2 chip area. The chip
achieved a saturated output power of 32 dBm with a
gain of 13 dB and a power added efficiency close to
30% in a 6 dB of output power back-off at 28 GHz.
In [62], a fully integrated Doherty PA monolithic
microwave integrated circuit with post-distortion
linearization at millimeter-waves was presented.
The Doherty PA MMIC, using a 0.15-Âµm GaAs HEMT
process, achieved a small signal gain of 7 dB from
38 to 46 GHz and with a compact chip size of 2 mm2.
The saturation output power of the Doherty amplifier was 21.8 dBm at 42 GHz. After gate bias optimization, the quasi Doherty amplifier with Class-AB
carrier amplifier and Class-C peaking amplifier was
selected to improve efficiency and linearity simultaneously. IMD3 of the quasi Doherty amplifier could
be improved 18 dB at 42 GHz and the drain efficiency improved 6% at 6-dB output back-off compared
with the balance amplifier operation.
IEEE CIRCUITS AND SYSTEMS MAGAZINE	

61
IEEE Circuits and Systems Magazine - Q4 2020

Table of Contents for the Digital Edition of IEEE Circuits and Systems Magazine - Q4 2020
