IEEE Circuits and Systems Magazine - Q4 2021 - 27

A binary weight network (BWN) is trained for low-power speech recognition.
This BWN can significantly reduce the operations of multiplication and weight
memory access, while maintaining high recognition accuracy.
the windowing module, which is used to minimize the
disruptions of each frame and increase the continuity
of each speech data. The fourth is the FFT module. In
this stage, the N samples of each frame are converted
into the frequency domain by the FFT operation. Next is
the Mel filter module, which is used to more intuitively
represent the energy in various frequency regions. In
the latest MFCC extraction designs, the 20~40 Mel filters
are used for the Mel filter module. Because the Mel filter
bank scales are strongly correlated with each other, the
DCT of logarithm filter bank energies can be calculated
in the typical MFCC extraction.
The top architecture of a typical DNN based speech
keywords recognition system is shown in Fig. 1, which
mainly consists of two modules: the MFCC feature extraction
module is used to extract the features of the
input speech, which are 26 Mel coefficients for each
speech frame in this work; the DNN classification module
is used to classify the speech features extracted by
the MFCC module and determine which keyword it is
(or an unknown word). In this work, we have trained
a binary weight network (BWN) for low-power speech
recognition. As shown in Fig. 1, the BWN is composed
of four convolution layers and two fully connected layers.
During the training process, the weights of the gradient
calculations in the entire forward transfer and
back propagation are binarized to 1+ or
-1 . The size
of each layer of convolution kernel is 33 ,# the number
of convolution kernels is 20, 24, 16, and 12 respectively.
In BWN, the weight is binarized to 1 bit, while
the data is maintained as 16 bits. Similar to the binary
neural network (BNN) adopted in work [9], since the
weights of BWN are also binarized to 1 bit, the multiplication
operations are almost eliminated and the
weight memory access can be significantly reduced in
BWN. However, since the bit-width of the data in BWN
is not binarized to 1 bit, so that more feature characteristics
of the input voice can be retained, which
makes an improved recognition accuracy in BWN.
III. System-Architecture-Circuits Co-Design With
Approximate Computing for MFCC
A. 8-Stage Radix-2 Single-Path Delay Feedback
FFT Structure for Speech Keywords Recognition
In the typical design, the frame unit is used to output per
frame data with frame overlap, and output a frame of
FOURTH QUARTER 2021
512 points (32 ms) in the time domain with 256 points
form the previous and 256 points form the next frames.
A 512-point FFT is required at a 16 kHz sampling rate
and frames of 32 ms with a 16ms step in our previous
work [12]. However, only a 256-point FFT can be used to
process the same frequency-domain transform operation
for one frame at an 8 kHz sampling rate. A 256-point
FFT results in a memory compressed by 2× and operations
reduced by 4× compared with a 512-point FFT. As
shown in Fig. 2, under the different background noise
levels and different noise types, mixed training operations
are implemented. The MFCC extraction at an 8 kHz sample
rate with a 256-point FFT can maintain the same accuracy
level compared with a 512-point FFT at a 16 kHz
sample rate.
In our hardware circuit design, we use the Radix-2
FFT structure to implement a 256-point FFT at an
8 kHz sample rate. The traditional FFT structure can
be implemented in parallel, serial pipeline, or loop, as
shown in Fig. 3. In the parallel structure design, each
stage is configured with 128 butterfly operation units.
A total of 1024 butterfly units are required to complete
a 256-point FFT, each unit is equipped with 4 multipliers
and 6 adders. As shown in Fig. 3(a) the butterfly
units operation results in the intermediate stage can
be directly sent to the next stage for the next stage of
butterfly operations without memory. In the serial pipeline
structure design, only one butterfly operation unit
90
87
84
81
78
75
-0.95%
dB
72
05 10
15
Signal to Noise Ratio
Figure 2. MFCC extraction accuracy at different sampling
rates.
IEEE CIRCUITS AND SYSTEMS MAGAZINE
27
20
-0.04%
-0.15%
-0.42%
-0.61%
16 kHz
8 kHz
Accuracy (%)
IEEE Circuits and Systems Magazine - Q4 2021

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