IEEE Circuits and Systems Magazine - Q4 2021 - 28

An 8-stage serial pipeline FFT design based on Radix-2 Single-path Delay
Feedback structure is utilized for MFCC. This FFT design is further optimized
with the fine-grained bit-width stepwise quantization.
needs to be configured at each stage in a serial FFT
structure and a total of 8 butterfly units are required to
complete the 256-point FFT, as shown in Fig. 3(b). The
operation results of each stage are serial and need to
be temporarily stored in independent memory for the
next stage of butterfly operations. The serial FFT structure
is more complex and slower than the parallel FFT
structure, however, its number of butterfly units is only
1/128× of that in the serial pipeline FFT structure. In the
loop FFT structure, only one butterfly operation unit is
needed to implement a complete serial FFT operation.
As shown in Fig. 3(c), a loop FFT structure includes one
stage of butterfly operation unit and two independent
depths of 256 dual-port memory. The control unit determines
the specific stage that the current butterfly
operation is performing and the direction of the data
flow. This two-stage serial-pipeline Radix-2 FFT structure
can maximize the use of hardware resources. However,
compared with the serial pipelined structure, this
structure requires a larger size of memory and reduces
the throughput to 1/8×.
In the proposed MFCC architecture for speech recognition,
the input data of the FFT structure is normalized
to the range of [, ],11
-+ which uses a 10-bit fixed-point
Control Unit
FFT Input 256
BF2
BF2
Stage 1
Register Buffer 256
BF2
BF2
Stage 8
Register Buffer 256
FFT Output 256
(a)
Stage 1
128D
x(n)
BF
2
W128
Stage 2
64D
BF
2
W64
Stage 3
32D
BF
2
W32
Stage 4
16D
BF
2
W16
Control Unit
(d)
Figure 3. Four different FFT structures: (a) Parallel FFT structure; (b) Serial pipelined FFT structure; (c) Loop FFT structure;
(d) R2SDF-FFT structure.
28
IEEE CIRCUITS AND SYSTEMS MAGAZINE
FOURTH QUARTER 2021
Stage 5
8D
BF
2
W8
SRAM A
256
BF2
SRAM B
256
Address Generation Unit
(c)
Stage 6
4D
BF
2
W4
Stage 7
2D
BF
2
j
Stage 8
1D
BF
2
X(K)
BF2
Address Generation Unit
(b)
Control Unit
BF2
BF2
BF2
BF2
SRAM
SRAM
SRAM

IEEE Circuits and Systems Magazine - Q4 2021

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