A fine-grained reconfigurable approximate computing architecture with Dual-Vdd is firstly proposed to further reduce energy cost. Compared to state-of-the-art designs, the proposed MFCC performs up to 76.3% lower in power consumption. digital representation (sign bit: 1 bit, integer bit: 1 bit, decimal bit: 8 bits); the output data of the FFT structure is 16-bit. Compared with the loop structure, the series pipeline structure can realize data quantization stepwise because different BF2 units in each stage are provided. In this paper, we use an 8-stage serial pipeline FFT design based on the Radix-2 Single-path Delay Feedback (R2SDF) structure, as shown in Fig. 3(d). Since the speech data loaded into the FFT is 10-bit, we set the lower boundary of compression bit-width to 10-bit. Table I shows the resource occupation details of the R2SDF structure under different data bit-width selections, where the peak signalto-noise ratio (PSNR) is used to measure and evaluate the error level of the fixed-point FFT operation results compared