30 IEEE CIRCUITS AND SYSTEMS MAGAZINE FOURTH QUARTER 2021 10′b W 10′b/12′b/16′b D Parameter Buffer Encoder Data Buffer RA1 RA1 RA1 RA1 RA1 RA1 RA1 RA1 RA1 RA1 RA1 RA1 RA1 RA1 RA1 RA1 RA1 RA1 RA1 RA1 FA FA FA RA2 RA2 RA2 RA2 3′b FA FA 13/9/7 FA RA2 RA2 Control Result Buffer (a) 1-bit FA Cout 1-bit FA 1-bit FA 1-bit FA 1-bit FA Ci 4′b/6′b/8′b 5′b/5′b/7′b (b) Figure 5. (a) Approximate multiplication architecture with Dual-Vdd for FFT; (b) Approximate addition architecture with Dual-Vdd for FFT. (Continued) 1-bit ORA 1-bit ANDA 1-bit FA 1-bit ORA 1-bit FA 1-bit ORA 1-bit FA 1-bit ORA 000:HDL = 0; VDL = 0 001:HDL = 2; VDL = 7 010:HDL = 2; VDL = 8 011:HDL = 2; VDL = 9 100:HDL = 2; VDL = 10 101:HDL = 3; VDL = 7 111:HDL = 3; VDL = 8 110:HDL = 3; VDL = 9