FOURTH QUARTER 2021 IEEE CIRCUITS AND SYSTEMS MAGAZINE 31 FA RA1 RA2 RA3 !HDL_enable~!en_1 HDL_enable~en_1 !VDL_enable (c) VDL_enable !en_2 en_2 VddH:0.6v Ci VddH:0.6v A B B Ci A B Ci Ci A Ci A B B A B Ci B 1 1-bit FA (d) Figure 5. (Continued) (c) The gate-level circuit representation of the cells; (d) Transistor-level circuit representation of the cells. 00 01 01 10 1 00 01 01 01 1 1 A Sum 1-bit AND FA Truth Table (None Carry-In) 1-bit ORA ORA Truth Table (None Carry-In) VddH:0.6v A B B Co A A Co′ Co B Sum′ Sum A A VddH:0.6v B B A VddL:0.4v VddL:0.4v