adder (ORA) according to whether discarding the horizontal carry or not; the reconfigurable adder 2 (RA2) can be configured as an FA and an AND-gate based adTable II. Configurations of proposed multiplier with FA, RA1 and RA2. Multiplier 10 × 10 bits 12 × 10 bits 16 × 10 bits FA 20 24 32 Number of Cells RA1 34 38 46 RA2 6 6 6 der (ANDA) according to whether discarding the vertical carry or not. For the trade-off between accuracy and power reduction, HDL and VDL can be dynamically reconfigured to satisfy different calculation requirements. When an ORA or an ANDA is working, an FA can be rejected directly by system clock gating, and only a little leakage power is required. Besides, we propose a precision reconfigurable approximate addition architecture based on Dual-Vdd. For the 8-stage pipelined FFT, the bit-width configuration of each type of adder is shown in Fig. 5(b). Fig. 5(b) shows the proposed approximate addition architecture consisting of the FAs for the most significant bits (MSBs) 0.4 0.332 0.3 63.9% 0.2 84.9% 0.12 0.1 0.05 1 FA ORA (a) 35 40 30 25 20 15 10 5 Precise Multiplier Proposed (Approximate) (c) Proposed (Dual-Vdd) 32.76 36.3% 20.87 18.61 43.2% 300 250 200 150 100 50 Precise FFT Module Proposed (Approximate) (d) Figure 6. Power consumption breakdown and analysis: (a) 1-bit adder; (b) proposed approximate adder; (c) proposed approximate multiplier; (d) the adopted FFT module. 32 IEEE CIRCUITS AND SYSTEMS MAGAZINE FOURTH QUARTER 2021 Proposed (Dual-Vdd) 500 400 450 350 306 262 496 38.3% 47.2% ANDA Precise Adder Proposed (Approximate) (b) Proposed (Dual-Vdd) 7 8 6 5 4 3 2 7.34 30.1% 5.13 39.4% 4.45 Power (nW) Power (nW) Power (nW) Power (nW)