IEEE Circuits and Systems Magazine - Q4 2021 - 33

and the RAs for the LSBs. As shown in Fig. 5(c), When
en_1 is 0, RA1 is configured as an FA, otherwise, it is
configured as an ORA and the carry is truncated. When
en_2 is 0, RA3 is configured as an FA. On the contrary,
when en_2 is 1, RA3 is configured as an ORA, and the
carry is generated by an ANDA and passed to the higher
bit. For other FFT pipelining levels, adders with different
bit-width have corresponding configurations. Therefore,
the precision reconfigurable approximate adder
reduces a lot of power consumption by configuring partial
FAs as ORAs/ANDAs.
Since the ORA does not have carry propagation
and the ANDA has a relatively short critical path compared
to the FA, the critical path delay of the multiplication
and addition can be reduced. Thus, we adopt a
Dual-Vdd method to reduce the power consumption of
the whole approximate multiply-add architecture. As
shown in Fig. 5(d), the FA uses a high power supply voltage
(VddH), the ORA and ANDA use a low-power supply
voltage (VddL). Taking the approximate addition
architecture with the 8 LSBs are the ORA/ANDA and the
8 MSBs are the FA. And, taking the approximate multiplication
architecture with the setting of HDL3= and
9
one second. The input speech data contains necessary
segments and redundant segments. The necessary segment
has a very important impact on the recognition
accuracy, while the redundant segment has less impact.
The redundant speech segments will cause great waste
of energy if both segments are processed by using the
operations with the same level of precision. Adaptively
tuning the hardware precision according to the processed
data can result in a significant power saving for
the MFCC module.
In order to achieve precision self-adaptive MFCC,
VDL= as an example, the power reduction has been
evaluated on TSMC 22 nm technology, as shown in Fig. 6.
The comparison results show that, compared to the 1-bit
FA, the power consumption of the ORA and ANDA can be
reduced by 63.9% and 84.9%, respectively. The comparison
of different addition architectures is shown Fig. 6(b).
The results show that, compared to the full-precision addition
architecture, the power consumption of the proposed
approximate addition can be reduced by 30.1%.
Compared to the full-precision multiplication architecture,
the power consumption of the proposed approximate
multiplication can be reduced by 36.3%, as shown
in Fig. 6(c). To get the most suitable value of VddH/VddL,
we perform the Monte Carlo simulation in HSPICE. In order
to find the most suitable value of VddL, we take the
step size of VddL as 0.35 V while the VddH is fixed as
0.6 V. By comparing the critical path delay of each part, we
can get the point where the delay of precise addition is
equal to that of the imprecise addition. In this work, the
VddL is configured as 0.4 V. With this configuration, the
power consumption is reduced by 40% compared to the
typical standard full-precision structure under the TSMC
22 nm ULL process. The power consumption of the FFT
module can be reduced by 47%, as shown in Fig. 6(d).
C. Precision Self-Adaptive MFCC Architecture
With Proposed Approximate Computing
Since the speech lengths of different keywords are different,
in order to accommodate different keywords recognition,
the input speech length is always defined as
FOURTH QUARTER 2021
we added an SNR unit and a VAD unit in the proposed
MFCC feature extraction architecture. With these two
units, the MFCC feature extraction module can be dynamically
reconfigured to use two calculation modes
with different hardware settings according to the intensity
of the background noise. In this work, the simple
VAD unit is used as a turn-on/turn-off switch for the
MFCC extraction module. The boundaries between
the necessary and redundant speech segments are
quite obvious from the input speech data under low
background noise with high SNRs. However, when the
background noise goes to high and the SNR is low,
detecting the boundaries between the two segments
will be extremely difficult by using a simple VAD unit.
The implementation of the simple VAD unit is shown
in Equation 1, where b is the ratio of N (the number
of :, )Xi n01Xii
2
= +
points exceeding " 0 " to the total
number of one frame points n. At the front end of the
VAD unit, a simple SNR unit is also adopted to approximately
predict the intensity of the input speech background
noise. The SNR unit only calculates once every
minute in this work, which can support extremely frequent
background noise switching. The implementation
of the simple SNR unit is shown in Equation 2, which
calculates the short-time energy. Based on the output
90
87
84
81
78
75
72
69
05 10
15
Signal to Noise Ratio
Figure 7. MFCC extraction accuracy at different model.
IEEE CIRCUITS AND SYSTEMS MAGAZINE
33
20
-2.14%
-4.03%
HP
LP
-7.96%
dB
Accuracy (%)
IEEE Circuits and Systems Magazine - Q4 2021

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