IEEE Circuits and Systems Magazine - Q4 2021 - 35

results of the SNR unit, the proposed MFCC extraction
module can be dynamically reconfigured
to work in a low-power consumption (LP)
mode or a high performance (HP) mode. When
the SNR is high, the LP MFCC extraction model
is used that all noise frames are refused by the
simple VAD unit and only padding " 0 " as MFCC
extraction results, which can reduce the power
consumption by up to 40% less power with no
accuracy loss. Otherwise, when the SNR is low,
the HP MFCC extraction model is used to process
both voice frames and noise frames just
like the traditional MFCC extraction.
b Nn 100)
a=+ g XX Xn
1
2
2
2
2
= /%
(1)
(2)
The speech dataset used in this paper comes
from Google Speech Commands Dataset (GSCD),
and the background noise comes from the standard
noise database Noise-92 database [15],
which includes 15 different types of noise such
as babble, pink, and white. The 70%, 15% and
15% of the database are configured as the training
dataset, validation dataset and test dataset,
respectively. The training dataset and validation
dataset are put together and used to train
the DNN to generate a set of corresponding
configurations (weight), and then use this set of
weights for different SNR levels keyword recognition
accuracy tests. The experimental results
in Fig. 7 show that, when the SNR is higher
than 15 dB, both the HP mode and LP mode can
maintain the same high recognition accuracy.
However, when the SNR is lower than 15 dB,
the accuracy using LP mode decreases rapidly.
Therefore, we use the LP/HP mode for MFCC
extraction module when the SNR is above/below
15 dB. The SNR unit is used to determine
whether the background noise is higher than
15 dB, and the VAD unit is turned on only in
the LP mode. When the output result of the SNR
unit is low, the control signal from the SNR unit
will turn off the VAD unit.
The proposed MFCC architecture with precision-adaptive
approximate computing is shown
in Fig. 8, which includes a simple SNR unit, a
simple VAD unit, a Clock Gating unit, and a typical
MFCC extraction module without DCT unit.
The proposed architecture includes four signal
flows: 1) the SNR control flow; 2) the VAD control
flow; 3) the Clock Gating control flow; and 4)
the data flow. The input speech signals are first
FOURTH QUARTER 2021
IEEE CIRCUITS AND SYSTEMS MAGAZINE
35
Frame1
Frame48
Frame2
25
26
Traditional
MFCC Extraction
2
1
1 2
4849
Each Frame Requires MFCC Feature Processing,
Even a Redundant Frame
HP Mode
Figure 8. (Continued).
2
1
1 2
Frame49
40% Less
Power With No
Accuracy Loss
Proposed
MFCC Extraction
4849
A Redundant Frame Does Not Require Any
Operation, Padding 0 as the Direct Result
LP Mode
25
26
Frame1
Frame2
Frame48
Frame49
26 dim/frame
26 dim/frame

IEEE Circuits and Systems Magazine - Q4 2021

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