IEEE Circuits and Systems Magazine - Q4 2021 - 36

sent to the simple SNR unit, the simple VAD unit, and the
Pre-Emphasis unit. The simple SNR unit based on shortterm
energy is used to grade the background noise level
and determines the computing mode of the MFCC architecture.
The simple VAD based on the zero-crossing rate
is used to determine whether the current frame is the
Table III.
Parameter statistics of the proposed MFCC extraction.
Characteristics
Value
Bit-width
Sampling rate
Frame
FFT points
FFT bit-width stepwise
Mel filters
Tech
Voltage
Memory
Core size
Frequency
Power
8-16 bits
8 kHz
32 ms (16 ms step)
256
10-10-10-12-12-12-16-16
26
22 nm
0.6 V/0.4 V
0.953 KB (double port: 0.547 KB,
single port: 0.406 KB)
0.047 mm2
150 kHz
1.21 nW@HP; 0.728 nW@LP
voice (necessary) or the noise (redundant). Compared
to the typical VAD design, the VAD unit adopted here
is only used to ensure a high recognition accuracy of
voice-to-voice but not noise-to-noise. The clock gating
unit controls the driven clock of each unit. As shown in
Fig. 8, when a frame of the input speech is received, the
simple SNR unit will process the input speech frame and
determine whether the background noise of the current
frame is low (in this work, the SNR is higher than 15 dB)
or high, and set the SNR control signal. When the SNR
control signal is set to 1, the simple VAD unit is enabled;
the proposed MFCC architecture will be configured to
use the LP mode. In this case, the rest modules of the
MFCC architecture are controlled (turned on/off) by the
Clock Gating unit. When a redundant frame segment is
detected, features with the value of 0 are padded into
the 26 MFCC features of the current speech frame. In HP
mode, the SNR control signal is set to 0, the rest modules
of the MFCC architecture are turned on. In this case, the
sample VAD unit is turned off.
Besides, the proposed MFCC extraction architecture
is also optimized from the following aspects: 1) We replace
the multiplication operations of the Pre-emphasis
unit with the right shift and addition operations (by setting
the filter coefficient 0.9375 to /);
15 16 2) The Frame
unit is composed of only one buffer to store 128 points
90.9%
87.9%
5.3 µW
5.1 µW
86.2%
88.7%
88.6%
0.8%
76.3%
2.8 µW
1.21 µW
0.72 µW
JSSC20 [13]
TCAS-I 20 [12]
(MFCC:HP)
Register
26.1%
Combinat
Orial
18.5%
Memory
53.2%
Leakage
42.7%
PowerBreakdown of theProposedMFCC
(MFCC:HP Mode)
[TSMC22 µmHVT at 0.6 V, 150kHz]
Figure 9. Power reduction result of the proposed MFCC.
36
IEEE CIRCUITS AND SYSTEMS MAGAZINE
FOURTH QUARTER 2021
Dynamic
57.2%
TCAS-I 20 [12]
(MFCC:LP)
This Work
(MFCC:HP)
Switch
0.01%
Register
29.1% Combinat
Orial
10.3%
Memory
60.6%
Leakage
67.7%
PowerBreakdown of theProposedMFCC
(MFCC:LP Mode)
[TSMC 22 µmHVT at 0.6 V,150kHz]
This Work
(MFCC:LP)
Dynamic
32.2%
Switch
0.01%
74%
2.4%
Accuracy
Power

IEEE Circuits and Systems Magazine - Q4 2021

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