IEEE Circuits and Systems Magazine - Q4 2021 - 38

trained. Different SNRs include: 0 dB, 5 dB, 15 dB, 20 dB
and clean, and the different SNRs are averagely mixed,
that is, each account for 20%.
Comparisons with the state-of-the-art MFCC designs
for speech keywords recognition are shown in Table IV.
The DNN structure used in this paper is BWN and FC
(fully connected), the weight bit-width of DNN is 1 bit,
and the data bit-width of DNN is 16 bits. Compared to
the work [8], the power consumption of our work can
significantly be reduced by 77.2% and 86.3% with HP
mode and LP mode, respectively. Compared to the
work [9], our work can reduce the power consumption
by up to 86.8% (in LP mode) and 92.2% (in HP mode),
respectively. In work [9], the speech recognition system
is tested with only one keyword, therefore the recognition
accuracy is much higher than that of the work [8]
and our work. Compared to our previous work [12], this
work makes these contributions: Firstly, the proposed
MFCC can be dynamically configured to reduce unnecessary
calculations according to the effective duration
of each keyword; Secondly, the optimization using
8-Stage R2SDF-FFT and approximate computing architecture
and circuit with Dual-Vdd can further improve
the computing energy efficiency of FFT, while maintaining
the high accuracy of speech recognition. The experimental
results show that the consolidated accuracy obtained
under the mixed database is 85.97%. Compared
to work [12], this work can reduce the power consumption
by up to 74% (in LP mode) and 76.3% (in HP mode)
respectively, while the accuracy increased by 2.4% (in
LP mode) and 0.8% (in HP mode) respectively.
V. Conclusion
This paper proposes a precision adaptive MFCC for noiserobust
low-power speech keywords recognition. The
8-stage radix-2 single-path delay feedback FFT (R2SDFFFT)
with fine-grained bit-width quantization is utilized
to reduce the required memory size for FFT. Then, the
precision reconfigurable approximate multiplication and
addition architecture and circuit Dual-Vdd are proposed
to further improve the computing energy efficiency of
the R2SDF-FFT. The proposed MFCC architecture can
be dynamically configured to using the low-power consumption
(LP) mode and the high performance (HP)
mode according to different precision requirements and
different lengths of various speech keywords. The power
consumption of the MFCC for speech keywords recognition
can be greatly reduced to the greatest extent while
ensuring accuracy. The proposed approach is implemented
and evaluated on 22 nm technology. Compared to the
state-of-the-art designs, the proposed MFCC can reduce
the power consumption up to 76.3%, while the accuracy
increased by 0.8%.
38
IEEE CIRCUITS AND SYSTEMS MAGAZINE
Acknowledgment
This work is funded with the National Science and Technology
Major Project under Grant 2018ZX01028101-005
and National Natural Science Foundation of China under
Grant 62022041 and Grant 61904028.
Bo Liu (Member, IEEE) was born in
Taizhou, Jiangsu, China in 1984. He received
the B.S. and Ph.D. degrees in Electronic
Science and Engineering from
Southeast University in 2006 and 2013
respectively. He is currently an associate
professor of National ASIC system Engineering Research
Center, Southeast University. His research interests include
chip architecture design, reconfigurable computing,
approximate computing and related VLSI designs. He has
authored or coauthored more than 40 scientific papers in
the above research fields, and holds 1 US patent and over
30 Chinese patents. His research is supported by the National
Natural Science Foundation, National Science and
Technology Major Project, and National Key R&D Program.
Xiaoling Ding received the B.S. degree
in electronic information science and
technology from Henan University,
Henan, China, in 2019. She is currently
pursuing the M.S. degree in Integrated
Circuit Engineering from Southeast University,
Nanjing, China. Her current research interests
include speech recognition and low voltage circuits.
Hao Cai (Member, IEEE) received the
Ph.D. from TELECOM Paristech, Universite
Paris-Saclay, France, in 2013. From
2012 to 2015, he was involved in the European
EUREKA Program Catrene-RELY for
high-reliability nanoscale integrated circuits
and systems. He worked with the Department Communications
and Electronics, TELECOM Paristech as research
associate from 2013 and as the associate professor
from 2018. From February 2018, he is an Associate Professor
with National ASIC System Engineering Center, Southeast
University in Nanjing, China. He has authored or coauthored
more than 70 scientific papers. His research
interests include memory design, emerging computing and
ultra-low power emerging device-circuit interaction design.
Wentao Zhu received the B.S. degree in
electronic science and technology from
Chongqing University of Technology,
Chongqing, China, in 2017. He is currently
pursuing the M.S. degree in Integrated
Circuit Engineering from Southeast
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