IEEE Circuits and Systems Magazine - Q4 2021 - 42

VSS
VDD
φ2n
MN3
Coffset
A
MN2 MN1
MN6S
MN6
φ1n
VDD
E
MNT5 MN5
G
vin
S
MNSW
Figure 4. Bootstrapping circuit which avoids breakdowns.
D
φ2n
VSS
B
φ2p
MP6
MP4
reset opamp circuit [9] which sets
it in a unity-gain configuration. Yet
another method [10] replaces the
floating switches with resistors.
Amplifiers have finite gain and
bandwidth issues, and dc offset
as well as 1/f and thermal noise
and nonlinearity problems. Several
of these nonideal effects can
be mitigated by correlated double
sampling [11] and correlated level
shifting [12]. The former can cancel
the dc offset, and high-pass the
filter noise; the latter can reduce
the output swing of the opamp,
and thus also reduce distortion
and finite gain effects. An example
of a stage with correlated level
shifting is illustrated in Figure 5.
In conclusion, switched-capacitor circuits are a good
CC
CCLS
-
+
1
Vin
2,3 C1
1
C2
A1
-
+
A2
3
3
2,3
1
Figure 5. Amplifier stage with correlated level shifting.
next. The signal dependence of both Qch
and Ron
can
be reduced by making the gate-channel voltage have
a fixed value Vdd
(Figure 2). Another problem may be
that the clock voltage may be too low for turning on the
switch. This may occur if the circuit is powered by a battery,
or harvested energy. The clock voltage swing may
be doubled by the scheme proposed by Y. Nakagome et
al. and shown in Figure 3 [6]. Note that both the above
arrangements may lead to overload and breakdowns,
and have to be carefully examined. More complex switch
driver circuits which avoid breakdown problems have
also been found; a popular one is shown in Figure 4 [7].
There are also alternative strategies that completely
eliminate the floating switch. These include the switched
operational amplifier (opamp) circuit [8], which replaces
the switch with a short circuit, and disables the driving
amplifier during the discharging clock phase, and the
CL
option for the implementation of accurate analog signal
processing at low or medium frequencies. At high frequencies,
continuous-time circuits may be preferable.
References
[1] J. C. Maxwell, A Treatise on Electricity and Magnetism, vol. 2. Oxford:
Clarendon Press, 1873.
[2] D.L. Fried, " Analog sample-data filters, " IEEE J. Solid-State Circuits
(JSSC), vol. 7, no. 4, pp. 302-304, Aug. 1972. doi: 10.1109/JSSC.1972.1050305.
[3] R. Gregorian, K.W. Martin, and G.C. Temes, " Switched-capacitor circuit
design, " Proc. IEEE, vol. 71, pp. 941-966, Aug. 1983. doi: 10.1109/
PROC.1983.12700.
[4] G.C. Temes, " Simple formula for estimation of minimum clock
feedthrough error voltage, " Electron. Lett., vol. 22, pp. 1069-1070, Sept.
1986. doi: 10.1049/el:19860733.
[5] T. C. Carusone, D. Johns, and K.W. Martin, Analog Integrated Circuit
Design, 2nd ed. Hoboken, NJ: Wiley, 2012.
[6] Y. Nakagome et al., " Circuit techniques for 1.5-3.6-V battery-operated
64-Mb DRAM, " IEEE J. Solid-State Circuits, vol. 26, pp. 1003-1010, July 1991.
[7] M. Dessouky and A. Kaiser, " Very low-voltage delta-sigma modulator
with 88 dB dynamic range using local switch bootstrapping, " IEEE J.
Solid-State Circuits, vol. 36, pp. 349-355, Mar. 2001. doi: 10.1109/4.910473.
[8] M. Steyaert, J. Crois and S. Gogaert, " Switched-Opamp, a technique
for realising full CMOS switched-capacitor filters at very low voltages, "
in Proc. European Solid-State Circuits Conf., 1993.
[9] M. Keskin, U. Moon and G.C. Temes, " A 1-V 10-MHz clock-rate 13Bit
CMOS delta-sigma modulator using unity-gain-reset opamps, "
IEEE J. Solid-State Circuits, vol. 37, pp. 817-824, July 2002. doi: 10.1109/
JSSC.2002.1015678.
[10] G. Ahn et al., " A 0.6 V 82 dB delta-sigma audio ADC using switched-RC
integrators, " IEEE J. Solid-State Circuits, vol. 40, pp. 2398-2407, Dec. 2005.
[11] H. Yoshizawa and G.C. Temes, " Switched-capacitor track-and-hold
amplifiers with low sensitivity to opamp imperfections, " IEEE Trans. Circuits
Syst.-1, vol. 54, pp.193-199, Jan. 2007. doi: 10.1109/TCSI.2006.887454.
[12] B.R. Gregoire and U. Moon, " An over-60 dB true rail-to-rail performance
using correlated level shifting and an opamp with 30 dB loop
gain, " in Proc. IEEE Int. Symp. Solid-State Circuits, 2008, pp. 540-541.
42
IEEE CIRCUITS AND SYSTEMS MAGAZINE
FOURTH QUARTER 2021
IEEE Circuits and Systems Magazine - Q4 2021

Table of Contents for the Digital Edition of IEEE Circuits and Systems Magazine - Q4 2021
