IEEE Circuits and Systems Magazine - Q1 2021 - 12

correction step requires a multiplier, making the complexity similar to that of a second-order interpolator
(as shown in Fig. 5 for an LNS AU, to be analyzed later
in this section). Both Lagrange interpolation [164] and
Chebyshev polynomial approximation [20] (secondorder approximations) have been used to compute the
Gaussian logarithms. Second-order minimax polynomial
approximation has also been applied to compute the addition/subtraction in LNS [21]. Higher accuracy than what
can be found in standard FP arithmetic is achievable [20].
The approaches referred to above for subtraction in
the LNS domain work well, except in the critical region
^ m ! [-1, 0] h, due to the singularity of log 2 ^ 1 - 2 m h when
m " 0 (see Fig. 4 between m = -1 and m = 0 ) . Mathematical transformations, usually known as cotransformations, are used in this region. Using alternative functions defined in adjustable subdomains is one of these
transformations. An example of cotransformation is the
replacement of the computation of log 2 (1 - 2 m ) with two
successive subtractions [22], as expressed in (7). In this
equation, 2 k1 is individually chosen for each value, such
that the index m[1] for the inner subtraction falls on the
nearest modulo- T[1] boundary beneath m; T[1] is fixed
at a large value, with T representing the interval tables
that are stored. The value of the inner product for m[1]
can therefore be obtained directly from a lookup table
that covers the range -1 1 m 1 - T[1] at modulo- T[1]

p

q

Select q ≤ p; Subtract

λ

p

Range Shifter
Dual Mux

F

D

E

Multiply

P

Multiply

Carry Save Add

Carry Save Add

Carry Prop. Add

Figure 5. LNS addition and subtraction unit.
12

IEEE CIRCUITS AND SYSTEMS MAGAZINE

intervals. Since -T[1] # k[1] 1 0, 2 k1 . 1 and the magnitude of the index for the outer subtraction k 2 1 -1, the
computation is shifted away from the critical region [22].
2 p - 2 q = ^2 p - 2 q + k1h - 2 q + k2
2 k1 + 2 k 2 = 1 & k 2 = log 2 ^1 - 2 k1 h

(7)

A different type of cotransformation decomposes the
computation of G = log 2 ^1 ! 2 m h according to (8). The implementation in [23] approximates the cotransformation
log 2 ^1 - 2 m h / ^1 + 2 m h in a limited range 61, 2 h .
m
log 2 ^1 - 2 m h = log 2 1 - 2 m + log 2 ^1 + 2 m h
1+ 2

(8)

LNS AUs have been used in the design of configurable
and general purpose processors [21], [23]-[26].
The European Logarithmic Microprocessor (ELM)
is a 32-bit scalar microprocessor with a fixed-point
LNS-based AU ^b = 2 h, with numbers represented by a
sign bit and a fractional component of 23 bits [26]. This
processor implements addition and subtraction by
splitting the range of m in (6) into segments for every
increasing power of 2. In turn, these segments are split
into smaller intervals, and the function F = log 2 ^1 ! 2 m h
and its derivative (D) are stored in memory for each of
those intervals, as depicted in Fig. 5, with the values
of intermediate points estimated with a Taylor interpolation. To calculate the error for each interval, the
maximum error E is tabulated alongside F and D-this
error corresponds to when a point falls near the next
stored value tuple. A separate table of proportions
(P) stores the normalized shape of the common error
curve. Each proportion value will be 0 - when the required value is at the beginning of a segment-or up
to 1-when it is estimated by the interpolation. The
error is calculated by adding to the result of the interpolation the value of E # P. In Fig. 5, a range shifter is
inserted immediately after the selection of p for the
calculation of m. If m falls close to zero in the subtraction operation, p and m will be transformed into new
values, and m will be moved to the linear region by
applying the cotransformation (7) [15].
The ELM adopts a register-memory addressing mode
Instruction Set Architecture (ISA), with a single-level
cache integrated into the pipeline. The architecture includes 16 general-purpose registers, an 8 kbyte L1 data
cache, two adders/subtractors operating in three clock
cycles, and four combined multiplier/divider/integer
units operating in one clock cycle. Vector operations are
implemented in the ELM by using four identical functional units in parallel, requiring a data cache organization
in which four consecutive words are read out simultaneously. The ELM is designed and fabricated in 0.18 nm
FIRST QUARTER 2021
IEEE Circuits and Systems Magazine - Q1 2021

Table of Contents for the Digital Edition of IEEE Circuits and Systems Magazine - Q1 2021
