IEEE Circuits and Systems Magazine - Q1 2021 - 13

Logarithmic and Residue Number Systems mitigate the problem of the
carry chain underlying binary arithmetic, simplifying arithmetic operations
and exposing parallelism.
technology [26]. Its performance and accuracy, running
at 125 MHz, are evaluated against the TMS320C6711 contemporary Digital Signal Processor (DSP) [27], available
in the same technology and running at 150 MHz. The
TMS320C6711 is a Very Long Instruction Word (VLIW)
processor that is able to issue eight independent instructions every cycle, with two pipelined FP adders
and two other pipelined FP multipliers with a latency
of four cycles, and two integer units with a latency of
one cycle. It has been shown that the ELM is marginally
more accurate than the FP processor for additive operators, while multiplicative operators return exact results.
For a typical kernel, making equal use of each one of
the operators, LNS will incur roughly half the total error
of FP arithmetic. Moreover, notwithstanding the ELM
running at 5/6 of the clock speed of the FP processor,
the additive times were marginally better, the multiplications were 3.4 times faster, and the divisions and
square roots were many times faster in the former than
in the latter processor. Although LNS enables the design
of faster and, typically, more accurate processors than
those of FP arithmetic (the LNS implementation tends to
have smaller worst-case relative errors than those of FP
[28]), general purpose processors currently still adopt
the standardized FP, which also easily interfaces with
integer binary arithmetic.
Another LNS-based AU that adopts the hardwareefficient cotransformation (8) for subtraction in the
critical region, computing the second term of this
equation with a second-order polynomial, was proposed in [23]. The architecture of the LN¸ S-based AU
consists of four main blocks: i ) the pre- and postprocessing blocks, including the preparation steps of the
operations and the combination and/or selection of
the results produced by the two main interpolation
blocks; ii ) the main interpolator block that implements
the approximations for computing log 2 ^1 + 2 m h and
exponentiation on the complete range ^- 25, 0@, and
log 2 ^1 - 2 m h outside the critical region ^- 25, - 0.25@,
using second-order piecewise polynomial approximations; and iii) the critical region block used to calculate the logarithm of the cotransformation function
(8) for the critical region ^- 0.25, 0@ by approximating
the cotransformation function ^1 - 2 m h / ^1 + 2 m h using
a first-order polynomial and computing the required
log 2 function based on a range reduction technique
that normalizes the function argument to the range
FIRST QUARTER 2021

61, 2h. Since only one instruction is evaluated at a given time, interpolator data paths within the two parallel blocks ii) and iii) can be shared to obtain a more
compact design.
The LNS-based AU proposed in [23] was integrated
into the datapath of a custom 32-bit OpenRISC core [29]
using a CMOS 65 nm process. For comparison purposes,
an identical system was designed with featuring a standard IEEE 754 single-precision FP AUs with hardware
support for additions, subtractions and multiplications.
The error analysis show similar maximum and average
values to the ones achieved for addition and subtraction with the ELM. Executing also at a clock frequency of
125 MHz, the adder and subtractor have a latency of four
clock cycles, while the multiplier, divisor and square
root calculus exhibit a latency of one clock cycle. The
LNS-based adder/subtractor of this processor significantly reduces the circuit area required by the individual LNS units, mainly due to circuit sharing. Comparing
the energy efficiency of the LNS (per LOGarithmic Operation (LOGP)) and the FP-based AUs (per FLoating-Point
Operation (FLOP)) for a CMOS 65 nm process, addition
and subtraction in FP is approximately 3 times more efficient than in LNS (40 pJ/FLOP vs 130 pJ/LOGP), while
multiplication in LNS is approximately 1.5 times more
efficient (48 pJ/FLOP vs 30 pJ/LOGP), division is 17 times
more efficient (525 pJ/FLOP vs 30 pJ/LOGP), and square
root is 38 times more efficient than FP (609 pJ/FLOP vs
16 pJ/LOGP).
A combination of the LNS and FP representations
have been explored as an approach to designing hybrid AUs [30]. It enables, for example, the multiply
and divide operations to be computed using the LNS
format, while addition and subtraction are efficiently
performed in FP. The hardware for performing the FPto-LNS and LNS-to-FP conversions is embedded within
the hybrid AUs.

B. Residue Number Systems
The Chinese Remainder Theorem (CRT) was originally
proposed in the 3rd century AD [31]. In the 1950s, it became the support for the proposal of computer arithmetic based on the RNS [32]. The CRT states that given a moduli set " m 1, m 2, f, m n , of pairwise co-prime
numbers, i.e., the Greatest Common Divisor (GCD)
^m i, m j h = 1 for i ! j ( X m represents the residue of X
for the modulus m):
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