IEEE CIRCUITS AND SYSTEMS MAGAZINE 1 Program Memory + PC+1 CLK WB1 ′ Rin1 RA + enb′1 enb′2 WB1 WB2 RA RB ′ Rin1 ′ Rin2 Control en_conf′ Offset Constants Bank Register Data Bank Register Config. Ar ID B CLK AU1 AGU LU EX1 CLK B PC + 1 Figure 6. RDSP: RNS-based Reduced Instruction Set Computer RISC [167] -Address generation Unit (AGU); Logic Unit (LU). PC IF Ar AU2 Memory Data WB1 EX2/WB1 ac 16 FIRST QUARTER 2021 CLK WB2 WB2