IEEE Circuits and Systems Magazine - Q1 2021 - 17

range [0, 2 2n - 2], from the moduli subset " 2 n - 1, 2 n + 1 ,,
a one-digit error can be detected in the illegitimate
range [2 2n - 1, 2 3n + 1 - 2 n + 1 - 1]. It is worth noting that the
independence of residue digits in RRNS prevents a residue error in one channel from propagating to another.
A computationally redundant processing core with
high energy efficiency has been proposed [53]. The
computationally redundant energy-efficient processing for y'all (CREEPY) core comprises microarchitecture-,
ISA- and RRNS-centered algorithms and techniques to
efficiently perform computational error correction. This
work has shown significant improvements over a nonerror-correcting binary processing core. Although all
research on the design of cores based on the RRNS, the
microarchitectures abstract away the memory hierarchy
and do not consider the power-performance impact of
RNS-based memory addressing. Compared with a non-error correcting core that addresses memory in binary, direct RNS-based memory addressing schemes slow down
in-order/out-of-order cores. Novel schemes for RNS-based
memory access, extending low-power and energy-efficient
RRNS-based architectures, are proposed in [54].

by probabilities associated with bitstreams: p i is the
value of a stochastic bitstream I i defined as the ratio of
1 bits to the total number of bits. Considering Unipolar
Representation (UR), the stochastic bitstream values
are bound [0 : 1], while for Bipolar Representation (BR),
the values are bound by [-1 : 1], a result of applying the
scale factor 2 after a negative bias term (18). For example, a stream I containing 60% 1s and 40% 0s, as depicted
in Fig. 7, represents the numbers 0.6 and 0.2 in the UR
and BR, respectively.
UR = p ^ i h; BR = 2 # ^ p ^ i h - 0.5 h .

(18)

Neither the length nor the structure of I needs to be
fixed. The number represented by a particular stream is
not defined by the individual value of a bit in a specific
position; thus, SC relies on a nonpositional number representation. The randomization of the representation,
associated with the mapping from space to time, leads
to SC arithmetic that can be implemented with simple
logic circuits [56], [57].
For example, a single two-input logic gate can be
used to compute the product of the probabilities p # q
(Fig. 8). It is easy to show that for the UR, it is an AND
gate, while for the BR, it is an eXclusive-NOR (XNOR)
gate. A 2 : 1-bit multiplexer can be used to add two numbers in UR, as depicted in Fig. 8(b). The addition is
scaled by 1/2, as shown in (19).

C. Stochastic Number Representation
A stochastic signal is the result of a continuous-time stochastic process with two possible values, represented
by the symbols 0 and 1 [55]. Numbers are represented

p ^Oh = p ^ I 1 h p ^ I 3h + ^1 - p ^ I 3 hh p ^ I 2h
p (I 3) = 1
2

CLK

&
p ^Oh = 1 # ^ p ^ I 1h + p ^ I 2hh
2

SC
1 0 1 1 0 1

0 1 1

1 0 0

1 1

0

The correctness of the final result is impacted by the
correlation, or lack of randomness, between stochastic
bitstreams. For example, in the extreme case where the

Figure 7. Stochastic bitstream representing 0.6 in UR and
0.2 in BR.

l1
l1 0;1;1;0;1;0;1;0 (4/8)
l2 1;0;1;1;1;0;1;1 (6/8)

0;0;1;0;1;0;1;0 (3/8)

(19)

O

l2

(a)
l3

1;1;1;1;1;0;1;1 (7/8)
0;0;1;0;0;1;1;0 (3/8)

1

1;0;1;1;0;0;1;1 (5/8)

O

0

1;0;0;1;0;1;0;1 (4/8)
(b)

l1
l2

1;0;0;1;0;0;0;0;0;1;0;0;1;0;0;0 (4/16)

0;0;0;1;0;1;0;0;1;1;0;0;1;0;1;0 (6/16)

0;1;1;1;1;0;1;1;0;1;1;1;1;1;0;1 (12/16)
(c)

Figure 8. Multiplication and addition on SC. (a) Multiplication on UR. (b) Scaled adder on UR. (c) Multiplication on BR.

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