IEEE Circuits and Systems Magazine - Q1 2021 - 22

components, each corresponding to processing steps:
the Item Memory (IM), the Encoder and the AM. The IM
stores a sufficiently large collection of random hypervectors called items. This memory maps symbols to items
in the inference phase, as it was learned in the training
phase. The Data Processing Units (DPUs) of the Encoder
combines the input hypervector sequence according
to the application-specific algorithm to compose a single hypervector for each class. Finally, the AM stores
the trained class of hypervectors and delivers the best
prediction according to the Hamming distance ^d h h .
The inputs of the processor comprise the assignment
of symbols to an item in the IM, and the outputs comprise the assignment of class labels to the AM address,
all of which is enabled by the HD mapper.
An Application Specific Integrated Circuit (ASIC) for
the HDC-based programmable processor, with 2048bit vectors, was synthesized and implemented using
a 28 nm process with a high-k dielectric coupled with
metal gate electrodes (HK/MG) [73]. The chip showcases high energy efficiency, less than 1.5 J/prediction for
a comprehensive benchmark at clock cycle of approximately 2.5 ns. It rivals other state-of-the-art processors
targeting supervised learning, in terms of both accuracy
and energy efficiency.
E. Discussion and Approximate
Arithmetic Techniques
The LNS swaps the cost of addition/subtraction with the
cost of the multiplication/division operations, as well as
powers and roots, but it still leads to a large cost difference between these two operations categories. Although LNSs provide a similar range and precision to
those of FP, beyond the simplification of multiplication
and division to fixed-point addition and subtraction,
the FP number systems have become a standard, while
the LNS is mainly applied in niches. This occurs, for example, in signal processing, most recently in machine
learning, as shown in the next sections.
RNS belongs to the class of nonpositional representations exposing parallelism at a very fundamental
computing level to achieve high performance and at
the same time supports the design of reliable systems
(fault tolerance). Although the usage of RNS allows the
design of more energy-efficient systems, RNS does not
guarantee a decrement in cost or power consumption,
since the reduction operation has to be applied and the
sum of the residue bit-widths is typically the bit-width
of the equivalent fixed-point binary number. It can be
applied not only to designing hardware devices but also
to speeding up the execution of applications, such as
in cryptography, on traditional binary-based programmable systems (e.g., the massively parallel Graphic Pro22

IEEE CIRCUITS AND SYSTEMS MAGAZINE

cessing Units (GPUs)). However, RNS is not suitable for
designing comparison units, dividers and other nonlinear operations.
HDC is inspired by the attributes of neuronal circuits, including hyperdimensionality and (pseudo)
randomness. When employed on tasks such as learning and classification, HDC involves the manipulation
and comparison of large patterns (typically 10,000-bit
patterns) within memory. It allows systems to retain
memory, instead of computing everything they sense,
pointing more to a kind of Processing In-Memory (PIM).
The representation of the patterns, and the associated
arithmetic, does not assign any weight to the " digits "
according to their position in the pattern; thus, it is
also a nonpositional representation. A key attribute of
hyperdimensional computing is its robustness to the
imperfections associated with the technology on which
it is implemented. HDC improves with the advances in
memory technologies, replacing computation with the
manipulation of patterns in memory.
SC has shown promising results for low-power areaefficient hardware implementations, even though existing
stochastic algorithms require long streams that negatively impact the latency. Being another nonpositional
representation, SC improves the robustness of circuits
subject to random faults or component variability. Since
with SC, multiplications and additions can be calculated
using AND gates and multiplexers, significant reductions
in power and the hardware footprint can be achieved
in comparison to the conventional binary arithmetic
implementations. The significant savings in power consumption and hardware resources allow the design of
autonomous systems, such as embedded devices or for
computation on the edge.
SC is a good example of a representation that easily allows trading off the computation quality with the
performance and energy consumption by adjusting the
bitstream length. The idea of trading off accuracy with
performance and energy efficiency led to the approximate computing paradigm for designing circuits and systems [74]. This paradigm has been explored at several
levels, from basic circuits to components, processing
units, and programs. In particular, approximate arithmetic circuits have been proposed, including adders,
multipliers and dividers [75]. Both error characteristics,
such as the " error rate " and the " error distance, " and circuit measurements, such as the delay, cost and power
dissipation, should be considered for approximate circuits [75]. Approximate computing has been considered
for several applications with error resilience, such as
image processing and machine learning [76], [77]. Although most of the research on approximate computing
up to now has been focused on binary representation,
FIRST QUARTER 2021

IEEE Circuits and Systems Magazine - Q1 2021

Table of Contents for the Digital Edition of IEEE Circuits and Systems Magazine - Q1 2021