IEEE Circuits and Systems Magazine - Q1 2021 - 25

(Fig. 14(a)), while in the cross state, lights are routed to the
opposite (cross) arm output (Fig. 14(b)). A voltage signal
is applied to the switch to control the guidance of the input light to the desired output port. Theoretically, an HPP
switch could be operated at 400 GHz. However, the speed
of the whole system is limited by the speed of the modulators and photodetectors, as well as the electronic circuit
used to control the routing [94].
As discussed before, RNS arithmetic is applied digitwise; thus, independently for each digit, a number of
those switches are interconnected to perform the computation. This is necessary to make systems scalable,
since the number of switches grows with the square of
the number of bits. For example, for modular addition,
the shifting RNS adder explores the shifting property:
a modulo m adder requires a set of diagonally aligned
m - 1 HPP switches per each of the ^m - 1 h levels, with
^ m - 1 h2 switches in total. For example, Fig. 15(a) illustrates an adder modulo m = 5, requiring 42 switches
organized in 4 levels. When computing x + y, x can be
represented by the input light source, while y specifies
electrically the number of levels in which the switches
are in the cross state (in the example, levels 1 to 3 for
adding 3). For this shift-level selection, TC is used to enable level switching in the RNS channels, as presented
in Section II-B.
The ASD RNS adder uses a routing network as the
computing device (see Fig. 15(b)) [93]. To compute x + y,
x is represented by the input light source, and y, by the

switch states defined by binary electrical signals. By
storing the precalculated states that satisfy the all-to-all
nonblocking routing network in an Look up Table (LUT),
the input light is routed to the resulting output port.
Fig. 15(b) depicts a design for m = 5 and the light path used
to calculate, as in the previous example, 4 + 3 5 = 2,
now through an ASD network. A modulo m ASD RNS
adder requires ^m - 1 h2 / 2 + 2 switches (for odd m). If
the number of switches required by the ASD RNS adder
is less than that for the shifting RNS adder, then more
complex electronic control circuitry, typically including LUTs, is required.
Integrated nanophotonic RNS-based arithmetic processors exhibit a very short computational execution
time, achieved by optical propagation through an integrated nanophotonic router, on the order of dozens of
picoseconds. In comparison to All-Optical-Switch (AOS)
technology, also used for RNS-based arithmetic [96], integrated nanophotonics requires a relatively small area
due to the compact transistor size. The energy per operation, on the order of fJ/bit, has been shown to be orders
of magnitude lower [93].
C. Nanoscale Memristors and Hybrid Memories
Several alternatives to existing semiconductor memories, supported by advances in technologies and devices, have recently been proposed [97]. This has led,
for example, to the re-emergence of PIM architectures
based on Non-Volatile Memory (NVM) and 3D monolithic

Level 1
0

S4

1
3
4

S1

S15

S10

S14

S9

S5

S16

S11

S6

Level 4

S12

S7

S2

Level 3

S8

S3

2
Input

Level 2

1
2
3

S13

Optical Path

0

Output

4

Example Path
(a)

0
1
2
Input

3

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4
Optical Path

1
2

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3 Output
4

Example Path
(b)

Figure 15. On calculating 4 + 3 5 = 2 with modulo 5 adders. (a) RNS shifting adder. (b) RNS All-to-all Sparse Directional
ASD adder.

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