Table 8. Summary of FPGAs used and the algorithms/methods. Table 8. (Continued) Summary of FPGAs used and the algorithms/methods. Ref. Methods/Algorithms FPGA Use Ref. Methods/Algorithms FPGA Use [21] * STFT to obtain Doppler frequency * ETSM for narrow pulse digitization * Synthesize DDC in receiver * Sampling/ digitization process * Generating clock frequency, temporary storage, control and interface with PC [45] * FSLW with early termination * Chirp z-transform (CZT) * Algorithm implementation [2] * CSD and AD combined with * SSM * Clock frequency generation, digitized data storage [31] * Electromagnetic model for motion and vital sign * MLFM and MoM * Interfacing chip; through Ethernet; of control and baseband signals [76] * MRMN adaptive filter * Algorithm implementation [40] * Range compression for time-domain crosscorrelation * Algorithm implementation [79] * Reconfigurable PSK modulator * Modulator synthesis [74] * Digital modulator/ demodulator synthesis (BPSK modulator) * Modulator/ demodulator synthesis [68] * Modified OMP for CS reconstruction * FFT for correlation optimization * CG for large scale least square problem * Algorithm implementation * DDS combined with CORDIC to build a nonlinear distortion compensation scheme. * Distortion compensation scheme implementation [77] * GOA specifically MPSO * HSA for Mutation * Algorithm implementation [69] * New CS called BCoSaMP * RSPT * Algorithm implementation [78] * DDS based on LUT using wave compression and Taylor series * DDS synthesis [80] * DPC via FC using (FFT-OS) * DPC implementation [81] * LFM using FPGA based DDS * DDS implementation [82] * Waveform generation * Waveform generator synthesis [83] * FC based pulse compression and pulse Doppler processing * Algorithm implementation [53] * Noise jammer using pulsed noise jamming techniques. * Algorithm implementation [84] * Reconfigurable Modulators * Modulator synthesis [54] * FFT * CFAR * Ego-VC * Algorithm implementation [75] * APC specifically LSE * Algorithm implementation [44] * Two-stage reconstruction for CS * FSLW model * Algorithm implementation [52] 62 IEEE CIRCUITS AND SYSTEMS MAGAZINE (Continued) [49] Table Abbreviations: STFT: Short Time Fourier Transform ETSM: Equivalent Time Sampling Method DDC: Digital Down Converter BPSK: Binary Phased Shift Keying OMP: Orthogonal Matching Pursuit CS: Compressive Sensing FFT: Fast Fourier Transform CG: Conjugate Gradient DDS: Direct Digital Synthesis CORDIC: Coordinate Rotation Digital Computer MPSO: Modified particle Swarm Optimization HAS: Hamming Scan Algorithm Blocking Compressive Sampling Matching Pursuit: BCoSaMP RSPT: Radar Signal Processing Tool is a tool allows the designer to autogenerate fully optimized VHDL representation of BCoSaMP GOA: Global Optimization Algorithm LUT: Look Up Table DPC: Digital Pulse Compression FC: Fast Convolution OS: Overlap Save method LFM: Linear Frequency Modulation IFFT: Inverse Fast Fourier Transform CFAR: Constant False Alarm Rate Ego-VC: Ego-Velocity Compensation APC: Adaptive Pulse Compression LSE: Least Square Estimator FSLW: Four-Segment Linear Waveform Model. CZT: Chirp Z-Transform CSD: Complex Signal Demodulation AD: Arctangent Demodulation SSM: State Space Method MRMN: Modified Robust Mixed Norm MLFM: Multi Level Fast Multi Pole Method PT: Pan Tompkins Algorithm PSK: Phase Shift Keying MRCW: modified raised cosine waveform model FIRST QUARTER 2021