IEEE Circuits and Systems Magazine - Q1 2021 - 63

summarizes the state-of-the-art literature where FPGA
is used as a control/processing platform within a radarbased system for detection and monitoring of HR and
RR signals. FPGAs were used for signal pre-processing,
interfacing, as well as synthesis of certain mandatory
blocks. Besides that, it can also be applied for control,
digitization, signal generation, filtering, and demodulation. Another important function of an FPGA is to serve
as an implementation platform of novel algorithms for
HR and RR detection and monitoring. A summary of
these algorithms implemented on FPGA is also presented in Table 8. Many of these articles presented novel
FPGA designs and architectures to implement these algorithms. Some of these algorithms have been specifically implemented on FPGA for vital sign detection and
monitoring, while others have been developed for other
applications. However, most of them can be used for human detection with minor modifications. The features
of flexibility and reconfigurability in FPGAs have influenced designers to apply them not only as a verification
tool. Unlike ASICs, FPGAs can be used as an external
processor due to its better flexibility in reconfiguring its
design after implementation.
These FPGA-based implementations have been applied to different types of radars such as CW, FMCW,
UWB, and SFCW radar. More specifically, FPGA has been
used in the context of CW radar in [21] and [31]. For UWB
radar type, FPGA has been used in [21], [45] and [49].
Other pulse or impulse based radar also used FPGA
such as in [44], [53], [83] and [40]. Other state-of-the-art
articles in the table do not report the specific type of
radar where the reported synthesis/implementation of
the algorithm should be applied to.
The different functions of FPGA in the literature have
led to improved designs and validated implementation
in the detection and monitoring of HR and RR signals.
Whenever FPGA is adopted as the main platform for preprocessing or processing platform to extract RR and/or
HR information, certain parameters have been typically
focused on. These include the logic utilization, processing time/speed, latency, and accuracy by capitalizing on
its parallelism ability.
In [21], an FPGA was used to synthesize the digital
downconverter as well as for sampling and digitization
in the receiver part of the CW radar. Meanwhile, in the
UWB radar, the main use of FPGA is for generating the
clock frequency. Further processing of the UWB signal
was performed using PC, and FPGA was also used as interface and control module, and as temporary memory
of digitized data. Further improvement on this work was
performed by implementing the Doppler frequency extraction algorithm (STFT) on both radar types (CW and
UWB). In [74], an FPGA was used to synthesize the biFIRST QUARTER 2021

nary phase shift keying modulator/demodulator, which
is used for high range resolution detection. This implementation achieved a processing delay of around
2.569 ns. Besides that, reconfigurable phase shift keying
was synthesized using FPGA in reference [79].
An OMP algorithm was used for CS reconstruction
and was implemented on FPGA in [68] with a frequency
of 165 MHz and dictionary size 512 × 2048. This implementation achieved a 33-time increase in speed compared with previous designs, and the time required
for construction is around 391.8 ns with 1.2 × 10−3 accuracy. An illustration of the FPGA implementation and
interface of the algorithm and the design architecture is
shown below.
For the LFMCW in [52], a DDS algorithm combined
with CORDIC algorithm was used to build its nonlinear distortion compensation scheme, implemented
on an FPGA. This implementation improved the peak
side-lobe-ratio (PSLR) from 5.7 dB to 0.3 dB after applying the scheme. Next, the MPSO and HAS algorithms
implementation in [77] was performed on FPGA for radar applications. Another algorithm implementation
was developed and implemented on FPGA/GPU in [69].
The new CS reconstruction algorithm is called blocking
compressive sampling matching pursuit (BCoSaMP).
This work also introduced a signal-processing tool
(RSPT) which allowed designers to auto-generate fully
optimized VHDL representation of BCoSaMP by just
specifying several parameters. The reported FPGA implementation achieved 14-times faster processing over
the sequential implementation, while the GPU implementation achieved a 10.7-time speed-up. For samples
of 256, 512 and 1024, the throughput was 41025, 71793
and 116304 cycles, respectively, whereas the execution
time was 0.3487 ms, 0.61 ms and 0.988 ms, respectively.
The reported power consumption was 1960 mW. For
512 samples, the reported execution time was 3.1 ms,
0.3487 ms, and 0.442 ms for sequential, FPGA, and GPU
processing, respectively.
Another DDS implementation using FPGA was reported in [78]. This DDS has quadrature outputs, is based on
look up tables (LUT), and was designed with a 100 MHz
system clock. This design and implementation have spurious free dynamic range (SFDR) of 114 dB, which was
improved by 70 dB compared to traditional DDS. However, this was at the expense of increased logic utilization.
Next, a digital pulse compression algorithm was developed and implemented on FPGA in [80]. The use of FFTOS method to provide range resolution and to improve
the SNR was used in the DPC. The design achieved a
pulse compression gain of 27 dB and peak range side
lobe ratio of −56 dB. Meanwhile, a linear frequency modulation with 3 μsec pulse duration using an off the shelf
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IEEE Circuits and Systems Magazine - Q1 2021

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