IEEE Circuits and Systems Magazine - Q1 2021 - 64

FPGA based DDS was designed in [81]. The design and
implementation of the LFM consisted of a) Implementation of spot frequency generation (from 150 MHz to
350 MHz) using DDS AD9858; b) Design and realization
of LFM waveform using DDS for higher bandwidth. Simulation and results for a bandwidth of up to 200 MHz were
reported. In [82], a real time waveform generator suited
for wideband and supporting many popular modulation
schemes, was reported with its FPGA implementation.
This implementation was reported with a DAC capable
of up to 2.5 GSps and with reduced memory manipulation to change waveform by two to three orders of magnitude. The reconfiguration time was reported to be in
the range of hundreds of nano seconds, and the logic
utilization was less than 5% of modern FPGA resources.
As an example, for the CW, its memory requirement is
21.625 bytes and reconfiguration time is 120 ns.
In [83], a fast convolution processing-based pulse
compression and pulse Doppler processing were presented and implemented on FPGA. It resulted in improved target detection, range resolution, and speed estimation. Meanwhile, the work in [53] presents the FPGA
implementation of a noise jammer using the pulsed noise
jamming technique. The detection capability of the radar was reduced as the jamming to noise ratio (JSR) is
increased, and the radar was blind at a JSR of 30 dB.
Another reconfigurable modulator was reported and
implemented in [84]. The FPGA implementation was reported to be dynamically reconfigurable on the fly, and
features between 10.2% and 91.43% hardware resources
utilization, and 76.38% of power consumption reduction.
This is relative to the conventional non-reconfigurable
modulator design. The reconfiguration time requirement for amplitude modulation and frequency modulation was reported to be 121 ns, whereas for other modulation types, reconfiguration time takes 184 ns.
In [54], an FMCW radar for target detection via FFT
was designed. To alleviate the problem of constant false
alarm rate (CFAR), an ego-velocity compensation algorithm was introduced and implemented on an FPGA. The
total processing time reported was 60 ms with 97% reduction in CFAR upon the implementation of the algorithm.
The ego-velocity compensation logic reduction was decreased by around 96%, whereas in the case of CFAR, it
was reduced by 62%. Meanwhile, a series of radar signal
processing algorithms called adaptive pulse compression, and specifically the least square estimator, were
implemented on FPGA with coprocessor in [75]. Implementation was performed using different architectures;
(i) pipelining architecture, with an improved latency, but
at the expense of high logic utilization; (ii) distributed
memory architecture, which also has high logic utilization with better latency. This optimization architecture
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IEEE CIRCUITS AND SYSTEMS MAGAZINE

was reported to have reduced interval initiation of the
coprocessor by two, but increased hardware utilization
by 1.5 times, while at the same time, reduced latency of
the LS matrix when larger than 16 × 16.
A CMOS impulse radar with a two stage reconstruction algorithm for CS, and implemented on a FPGA, for
human respiration feature extraction was reported
in [44]. This algorithm featured 75% less complexity
compared with the OMP algorithm for CS reconstruction. When the implementation was designed with a 318 MHz
clock, a radar image resolution of 256 × 13 was achieved,
with a throughput (radar image rate) of 28.2 frames
per second and a latency of 35.4 ms. Figure 20 shows
the architectural blocks used for implementing the proposed OMP.
Meanwhile, another UWB radar and a respiration
model, called FSLW model, along with chirp-Z transform
to extract RR features, was presented in [45]. The FPGA
implementation of the algorithm resulted in a maximum
NSME of around 3.93% for the FSLW model and around
9.67% for the MRCW model. Even though the C-Z transform is three times more complex compared to the FFT,
the frequency estimation error is higher in the latter case.
In [2] and [49], the CSD and AD were techniques used
to improve detection accuracy of heart rate signals.
These methods were combined with SSM to further
increase the accuracy. The target subject was located
at a distance of 0.8 m and the results were reported for
more cases when the subject was holding its breath and
when breathing normally. When the subject is holding
its breath, maximum deviation of the HR was reported
to be 3.1% and 1.7% using direct FFT and using SSM,
respectively. However, this was minimized when using SSM-CSD and SSM-AD to 0.5%. The maximum SNR
was reported to be 50.2 when using SSM-AD, whereas
it was 8.4 when using direct FFT. In the case of the target breathing normally, the maximum deviation of HR
was reported to be 3.7% when using SSM and this was
minimized to 1.7% when using SSM-CSD and SSM-AD.
The maximum SNR was reported to be 32.6 when using
SSM-AD and was 20.4 when using AD only. The FPGA
was used in this work to generate the clock frequency,
to digitize the data stored, and for further processing.
In [31], an electromagnetic model of a walking human
and of human vital signs were developed and validated using a CW radar. The main function of the FPGA in
this design was an interfacing chip for the control and
baseband signal. Meanwhile, an MRMN adaptive filter
algorithm was developed and implemented on FPGA in
[76]. The post route and place implementation of this
FPGA indicated nearly 90% of reduction in resource utilization and nearly 2.6 times improvement in terms of
clock frequency and speed. In [40], a range compression
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