IEEE Circuits and Systems Magazine - Q2 2021 - 1

Circuits
and Systems
IEEE
MAGAZINE
Volume 21, Number 2
Second Quarter 2021
Features
4 FPGA Architecture: Principles and Progression
Andrew Boutros and Vaughn Betz
Since their inception more than thirty years ago, field-programmable gate arrays (FPGAs) have
been widely used to implement a myriad of applications from different domains. As a result of their
low-level hardware reconfigurability, FPGAs have much faster design cycles and lower development
costs compared to custom-designed chips. The design of an FPGA architecture involves many
different design choices starting from the high-level architectural parameters down to the transistorlevel
implementation details, with the goal of making a highly programmable device while minimizing
the area and performance cost of reconfigurability. As the needs of applications and the capabilities
of process technology are constantly evolving, FPGA architecture must also adapt. In this article, we
review the evolution of the different key components of modern commercial FPGA architectures and
shed the light on their main design principles and implementation challenges.
30 FPGA Acceleration for Big Data Analytics:
Challenges and Opportunities
Joost Hoozemans, Johan Peltenburg, Fabian Nonnenmacher,
©SHUTTERSTOCK.COM/EVGENIY JAMART
Ákos Hadnagy, Zaid Al-Ars, and H. Peter Hofstee
The big data revolution has ushered an era with ever increasing volumes and complexity of data
requiring ever faster computational analysis. During this very same era, CPU performance growth
has been stagnating, pushing the industry to either scale their computation horizontally using multiple
nodes in datacenters, or to scale vertically using heterogeneous components to reduce compute
time. However, networking and storage continue to provide both higher throughput and lower
latency, which allows for leveraging heterogeneous components, deployed in data centers around
the world. Still, the integration of big data analytics frameworks with heterogeneous hardware
components such as GPGPUs and FPGAs is challenging, because there is an increasing gap in
the level of abstraction between analytics solutions developed with big data analytics frameworks,
and accelerated kernels developed with heterogeneous components. In this article, we focus on
FPGA accelerators that have seen wide-scale deployment in large cloud infrastructures. FPGAs
allow the implementation of highly optimized hardware architectures, tailored exactly to an application,
and unburdened by the overhead associated with traditional general-purpose computer
architectures. FPGAs implementing dataflow-oriented architectures with high levels of (pipeline)
parallelism can provide high application throughput, often providing high energy efficiency. Latencysensitive
applications can leverage FPGA accelerators by directly connecting to the physical layer
of a network, and perform data transformations without going through the software stacks of the
host system. While these advantages of FPGA accelerators hold promise, difficulties associated
with programming and integration limit their use. This article explores the existing practices in big
data analytics frameworks, discusses the aforementioned gap in development abstractions, and
provides some perspectives on how to address these challenges in the future.
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48 A Survey of FPGA-Based Robotic Computing
Zishen Wan,* Bo Yu,* Thomas Yuang Li, Jie Tang, Yuhao Zhu,
Yu Wang, Arijit Raychowdhury, and Shaoshan Liu
Recent researches on robotics have shown significant improvement, spanning from algorithms,
mechanics to hardware architectures. Robotics, including manipulators, legged robots, drones,
and autonomous vehicles, are now widely applied in diverse scenarios. However, the high computation
and data complexity of robotic algorithms pose great challenges to its applications. On
the one hand, CPU platform is flexible to handle multiple robotic tasks. GPU platform has higher
computational capacities and easy-to-use development frameworks, so they have been widely
adopted in several applications. On the other hand, FPGA-based robotic accelerators are becoming
increasingly competitive alternatives, especially in latency-critical and power-limited scenarios.
With specialized designed hardware logic and algorithm kernels, FPGA-based accelerators can
surpass CPU and GPU in performance and energy efficiency. In this paper, we give an overview
of previous work on FPGA-based robotic accelerators covering different stages of the robotic
system pipeline. An analysis of software and hardware optimization techniques and main technical
issues is presented, along with some commercial and space applications, to serve as a guide
for future work.
75 The Evolution of Domain-Specific
Digital Object Identifier 10.1109/MCAS.2021.3056246
SECOND QUARTER 2021
Computing for Deep Learning
Stephen Neuendorffer, Alireza Khodamoradi, Kristof Denolf,
Abhishek Kumar Jain, and Samuel Bayliss
With the continued slowing of Moore's law and Dennard scaling, it has become more imperative
that hardware designers make the best use of domain-specific information to improve designs.
Gone are the days when we could rely primarily on silicon process technology improvements to
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IEEE Circuits and Systems Magazine - Q2 2021

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