IEEE Circuits and Systems Magazine - Q2 2021 - 11

logic utilization and a slow critical path due to connecting
many LUTs in series to compute carries for multi-bit additions.
Consequently, all modern FPGA architectures include
hardened arithmetic circuitry in their logic blocks.
There are many variants, but all have several common
points. First, to avoid adding expensive routing ports, the
arithmetic circuits re-use the LUT routing ports or are
fed by the LUT outputs. Second, the carry bits are propagated
on special, dedicated interconnect with little or
no programmability so that the crucial carry path is
fast. The lowest cost arithmetic circuitry hardens ripple
carry structures and achieves a large speed gain over
LUTs (.
34# for a 32-bit adder in [32]). Hardening more
sophisticated structures like carry skip adders further
improves speed (an additional 20% speed-up at 32-bits in
[33]). The latest Versal architecture from Xilinx hardens
the carry logic for 8-bit carry look-ahead adders (i.e. the
addition can only start on every eighth BLE), while the
sum, propagate and generate logic is all implemented in
the fracturable 6-LUTs feeding the carry logic as shown
in Fig. 7(a) [29]. This organization allows implementing
1-bit of arithmetic per logic element. On the other hand,
the latest Intel Agilex architecture can implement 2-bits
of arithmetic per logic element, with dedicated interconnect
for the carry between logic elements as shown in
Fig. 7(b). It achieves that by hardening 2-bit carry-skip
adders that are fed by the four 4-LUTs contained within
a 6-LUT [34]. The study by Murray et al. [32] shows that
the combination of fracturable LUTs and 2 bits of arithmetic
(similar to that adopted in Altera/Intel FPGAs)
is particularly efficient compared to architectures with
non-fracturable LUTs or 1 bit of arithmetic per logic element.
It also concludes that having dedicated arithmetic
circuits (i.e. hardening adders and carry chains) inside
the FPGA logic elements increases average performance
by 75% and 15% for arithmetic microbenchmarks and
general benchmark circuits, respectively.
Recently, deep learning (DL) has become a key workload
in many end-user applications, with its core operation
being multiply-accumulate (MAC). Generally, MACs
can be implemented in DSP blocks as will be described
in Section III-E; however low-precision MACs with 8-bit
or narrower operands (which are becoming increasingly
popular in DL workloads) can also be implemented efficiently
in the programmable logic [9]. LUTs are used
to generate the partial products of a multiplier array followed
by an adder tree to reduce the partial products
and perform the accumulation. Consequently, multiple
recent studies [35]-[37] have investigated increasing the
density of hardened adders in the FPGA's logic fabric to
enhance its performance when implementing arithmeticheavy
applications such as DL acceleration. The work in
[36] and [37] proposed multiple different logic block arSECOND
QUARTER 2021
chitectures that incorporate 4 bits of arithmetic per logic
element arranged in one or two carry chains with different
configurations, instead of just 2 bits of arithmetic in an Intel
Stratix-like ALM. These proposals do not require increasing
the number of the (relatively expensive) routing ports
in the logic clusters when implementing multiplications
due to the high degree of input sharing in a multiplier array
(i.e. for an N-bit multiplier, only 2 N inputs are needed
to generate N2 partial products). The most promising of
these proposals increases the density of MAC operations
by
17 . # while simultaneously improving their speed. It
also reduces the required logic and routing area by 8%
for general benchmarks, highlighting that more arithmetic
density is beneficial for applications beyond DL.
Cout[i]
prop
4-LUT
4-LUT
gen
4-LUT
Sum[i]
A[i]
B[i]
4-LUT
Cout[i-1]
(a)
Cout[i+1]
B[i+1]
A[i+1]
B[i]
A[i]
4-LUT
4-LUT
4-LUT
4-LUT
Sum[i+1]
Sum[i]
Cout[i-1]
(b)
Figure 7. Overview of the hard arithmetic circuitry (in red) in
the logic elements of (a) Xilinx and (b) Altera/Intel FPGAs.
A[i] and B[i] are the ith bits of the two addition operands A
and B. The Xilinx LEs compute carry propagate and generate
in the LUTs, while the Altera/Intel ones use LUTs to pass
inputs to the hard adders. Unlabled inputs are unused when
implementing adders.
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Cout[i ]
IEEE Circuits and Systems Magazine - Q2 2021

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