IEEE Circuits and Systems Magazine - Q2 2021 - 13

delay of passing through many routing switches. Some of
the routing architecture parameters include: how many
routing wires each logic block input or output can connect
to (),Fc
can connect to (),Fs
how many other routing wires each wire
the lengths of the routing wire segments,
the routing switch pattern, the electrical design
of the wires and switches themselves, and the number
of routing wires per channel [20]. In Fig. 9 for example,
,,
FF33
cs
== the channel width is 4 wires, and some
routing wires are of length 1, while others are of length 2.
Fully evaluating these trade-offs for target applications
and at a specific process node requires experimentation
using a full CAD flow as detailed in Section II.
Early island-style architectures incorporated only
short wires that traversed a single logic block between
programmable switches. Later research showed that this
resulted in more programmable switches than necessary,
and that making all wiring segments span four logic
blocks before terminating reduced application delay by
40% and routing area by 25% [40]. Modern architectures
include multiple lengths of wiring segments to better
match the needs of short and long connections, but the
most plentiful wire segments remain of moderate length,
with four logic blocks being a popular choice. Longer distance
connections can achieve lower delay using longer
wire segments, but in recent process nodes wires that
span many (e.g. 16) logic blocks must use wide and thick
metal traces on upper metal layers to achieve acceptable
resistance [41]. The amount of such long-distance wiring
one can include in a metal stack is limited. To best
leverage such scarce wiring, Intel's Stratix FPGAs allow
long wire segments to be connected only to short wire
segments, rather than function block inputs or outputs
[42]. This creates a form of routing hierarchy within an
island-style FPGA, where short connections use only the
shorter wires, but longer connections pass through short
wires to reach the long wire network. Another area where
hierarchical FPGA concepts are used within island-style
FPGAs is within the logic blocks. As illustrated in Fig. 4(d),
most logic blocks now group multiple BLEs together with
local routing. This means each logic block is a small cluster
in a hierarchical FPGA; island-style routing interconnects
the resulting thousands of logic clusters.
There has been a great deal of research into the optimal
amount of switching, and how to best arrange the
switches. While there are many detailed choices, a few
principles have emerged. The first is that the connectivity
between function block pins and wires ()Fc
can be
relatively low: typically only 10% or less of the wires that
pass by a pin will have switches to connect to it. Similarly,
the number of other wires that a routing wire can
connect to at its end ()Fs
can also be low, but it should
be at least 3 so that a signal can turn left, right, or go
SECOND QUARTER 2021
Figure 10. Different
implementations for SRAM-controlled
programmable switches using pass transistors (left), tri-state
buffers (middle), or buffered multiplexers (right).
IEEE CIRCUITS AND SYSTEMS MAGAZINE
13
straight at a wire end point. The local routing in a logic
cluster (described in Section III-A) allows some block
inputs and some block outputs to be swapped during
routing. By leveraging this extra degree of flexibility and
considering all the options presented by the multi-stage
programmable routing network, the routing CAD tool can
achieve high completion rates even with low Fc
and Fs
values. Switch patterns that give more options to the
routing CAD tool also help routability; for example, the
Wilton switch pattern ensures that following a different
sequence of channels lets the router reach different wire
segments near a destination block [43].
There are also multiple options for the electrical design
of programmable switches, as shown in Fig. 10. Early
FPGAs used pass gate transistors controlled by SRAM
cells to connect wires. While this is the smallest switch
possible in a conventional CMOS process, the delay of
routing wires connected in series by pass transistors
grows quadratically, making them very slow for large
FPGAs. Adding some tri-state buffer switches costs area,
but improves speed [40]. Most recent FPGAs primarily
use a multiplexer built out of pass gates followed by a
buffer that cannot be tri-stated, as shown in detail in
Fig. 4(b). The pass transistors in this direct drive switch
can be small as they are lightly loaded, while the buffer
can be larger to drive the significant capacitance of a
routing wire segment. Such direct drive switches create
a major constraint on the switch pattern: a wire can only
be driven at one point, so only function block outputs
and routing wires near that point can feed its routing multiplexer
inputs and hence be possible signal sources. Despite
this constraint, both academic and industrial work
has concluded that direct drive switches improve both
area and speed due to their superior electrical characteristics
[42], [44]. The exception is expensive or rare wires
such as long wires implemented on wide metal traces on
upper metal layers or the interposer-crossing wires discussed
later in Section III-G. These wires often have multiple
tri-state buffers that can drive them, as the cost of
Configuration
SRAMs
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