IEEE Circuits and Systems Magazine - Q2 2021 - 14

these larger programmable switches is merited to allow
more flexible usage of these expensive wires.
A major challenge for FPGA routing is that the delay of
long wires is not improving with process scaling, which
means that the delay to cross the chip is stagnating or
increasing even as clock frequencies rise. This has led
FPGA application developers to increase the amount of
pipelining in their designs, thereby allowing multiple
clock cycles for long routes. To make this strategy more
effective, some FPGA manufacturers have integrated
registers within the routing network itself. Intel's Stratix
10 device allows each routing driver (i.e. multiplexer followed
by a buffer) to be configured as a pulse latch as
shown in 6(b), thereby acting as a register with low delay
but relatively poor hold time. This allows deep pipelining
of interconnect without using expensive logic resources,
at the cost of a modest area and delay increase to the
routing driver [45]. Hold time concerns mean that using
pulse latches in immediately consecutive Stratix 10
routing switches is not possible, so Intel refined this approach
in their next-generation Agilex devices by integrating
actual registers (with better hold time) on only
one-third of the interconnect drivers (to mitigate the area
cost) [34]. Rather than integrating registers throughout
the interconnect, Xilinx's Versal devices instead add bypassable
registers only on the inputs to function blocks.
Unlike Intel's interconnect registers, these input registers
are full-featured, with clock enable and clear signals [46].
C. Programmable IO
FPGAs include unique programmable IO structures to
allow them to communicate with a very wide variety
of other devices, making FPGAs the communications
hub of many systems. For a single set of physical IOs to
programmably support many different IO interfaces and
standards is challenging, as it requires adaptation to different
voltage levels, electrical characteristics, timing
specifications, and command protocols. Both the value
and the challenge of programmable IO are highlighted
by the large area devoted to IOs on FPGAs. For example,
Altera's Stratix II (90 nm) devices support 28 different IO
standards and devote 20% (largest device) to 48% (smallest
device) of their die area to IO-related structures.
As Fig. 11 shows, FPGAs address this challenge using a
combination of approaches [47]-[49]. First, FPGAs use IO
buffers that can operate across a range of voltages. These
IOs are grouped into banks (commonly on the order of 50
IOs per bank), where each bank has a separate Vddio
rail
for the IO buffer. This allows different banks to operate
at different voltage levels; e.g. IOs in one bank could be
operating at 1.8 V while those in a different bank operate
at 1.2 V. Second, each IO can be used separately for single-ended
standards, or pairs of IOs can be programmed
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IEEE CIRCUITS AND SYSTEMS MAGAZINE
to form the positive and negative line for differential IO
standards. Third, IO buffers are implemented with multiple
parallel pull-up and pull-down transistors so that
their drive strengths can be programmably adjusted by
enabling or disabling different numbers of pull-up/pulldown
pairs. By programming some pull-up or pull-down
transistors to be enabled even when no output is being
driven, FPGA IOs can also be programmed to implement
different on-chip termination resistances to minimize
signal reflections. Programmable delay chains provide a
fourth level of configurability, allowing fine delay adjustments
of signal timing to and from the IO buffer.
In addition to electrical and timing programmability,
FPGA IO blocks contain additional hardened digital circuitry
to simplify capturing and transferring IO data to
the fabric. Generally some or all of this hardened circuitry
can be bypassed by SRAM-controlled muxes, allowing
FPGA users to choose which hardened functions are desirable
for a given design and IO protocol. Part ➄ of
Fig. 11 shows a number of common digital logic options
on the IO input path: a capture register, double to singledata
rate conversion registers (used with DDR memories),
and serial-to-parallel converters to allow transfer
to the fabric at a lower frequency. Most FPGAs now also
contain by-passable higher-level blocks that connect to
a group of IOs and implement higher-level protocols like
DDR memory controllers. Together these approaches allow
the general-purpose FPGA IOs to service many different
protocols, at speeds up to 3.2 Gb/s.
The highest speed IOs implement serial protocols,
such as PCIe and Ethernet, that embed the clock in data
transitions and can run at 28 Gb/s or more. To achieve
these speeds, FPGAs include a separate group of differential-only
IOs with less voltage and electrical programmability;
they can only be used as serial transceivers [50].
Just as for the general-purpose IOs, these serial IOs have
a sequence of high-speed hardened circuits between
them and the fabric, some of which can be optionally
bypassed to allow end-users to customize the exact interface
protocol.
Overall, FPGA IO design is very challenging, due to the
dual (and competing) demands to make the IO not only
very fast but also programmable. In addition, distributing
the very high data bandwidths from IO interfaces
requires wide soft buses in the fabric, which creates additional
challenges as discussed later in Section III-F.
D. On-Chip Memory
The first form of on-chip memory elements in FPGA architectures
was FFs integrated in the FPGA's logic blocks
as described in Section III-A. However, as FPGA logic
capacity grew, they were used to implement larger systems
which almost always require memory to buffer and
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