IEEE Circuits and Systems Magazine - Q2 2021 - 15

SECOND QUARTER 2021
IEEE CIRCUITS AND SYSTEMS MAGAZINE
15
2
1
Different Vddio Rails for the IO Buffers
in Different Banks (e.g., Vddio1 and Vddio2)
Each Pair of IOs can be Configured as
Two Single-Ended IOs or One Differential IO
Vddio
Out1EN
Vddio1
Logic
Blocks
Bank 1
In2
IO
Banks
Out2EN
5
Bank 2
To
Fabric
Double Data
Rate 1
Double Data
Rate 2
Single
Rate
Different Options For Capturing Input
Serial-ToParallel
From
IO
4
In
Delay
Config.
SRAMs
Programmable Delay Chain (PDC)
Out
Vddio2
IOs
Out2
PDC
-
PDC
Single-Ended
IO
Drive Strength
Config. SRAMs
Out1
In1
PDC
PDC
+
-
Single-Ended
IO
+
OutEN
Out
In
3
Programmable drive strength of output
buffers via multiple parallel pull up/down
transistors and programmable termination
resistances to minimize signal reflections.
Figure 11. Overview of the different techniques for implementing programmable IOs on FPGAs.
To/From Fabric
Input/Output Capture
Differential
IO
Impedance
Control

IEEE Circuits and Systems Magazine - Q2 2021

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