IEEE Circuits and Systems Magazine - Q2 2021 - 16

re-use data on chip, making it highly desirable to have
denser on-chip storage since building large RAMs out of
registers and LUTs is over 100# less dense than an (ASICstyle)
SRAM block. At the same time, the RAM needs of
applications implemented on FPGAs are very diverse,
including (but not limited to) small coefficient storage
RAMs for FIR filters, large buffers for network packets,
caches and register files for processor-like modules,
read-only memory for instructions, and FIFOs of myriad
sizes to decouple computation modules. This means that
there is no single RAM configuration (capacity, word
width, number of ports) used universally in FPGA designs,
making it challenging to decide on what kind(s) of
RAM blocks should be added to an FPGA such that they
are efficient for a broad range of uses. The first FPGA to
include hard functional blocks for memory (block RAMs
or BRAMs) was the Altera Flex 10 K in 1995 [51]. It included
columns of small (2 kb) BRAMs that connect to
the rest of the fabric through the programmable routing.
FPGAs have gradually incorporated larger and more diverse
BRAMs and it is typical for ~25% of the area of a
modern FPGA to be dedicated for BRAMs [52].
An FPGA BRAM consists of an SRAM-based memory
core, with additional peripheral circuitry to make them
more configurable for multiple purposes and to connect
them to the programmable routing. An SRAM-based
BRAM is typically organized as illustrated in Fig. 12.
It consists of a two-dimensional array of SRAM cells to
store bits, and a considerable amount of peripheral
circuitry to orchestrate access to these cells for read/
CS
Vdd
On Switch
Off Switch
SB
W
W
Output Crossbar
ExtAddrA
Log2(W)
WenA
W
WdataA
W
AddrA
Log2(D)+
Log2(W)+
W+1
Log2(D)
CB
Wen
Din
WL0A
WL1A
WL2A
WL3A
SRAM Cells
Din
SA
WD
BL
SA
BL
WD WD WD WD WD WD WD
SA
BL
SA
BL
SA
BL
SA
BL
SA
BL
SA
BL
W CSL
Sen
RdataA
Dout
Read/Write Circuitry B
BLB
General-Purpose Routing
WLB
BLA
BLA
Figure 12. Organization and circuitry of a conventional dual-port SRAM-based FPGA BRAM. The components highlighted in
blue are common in any SRAM-based memory module, while those highlighted in green are FPGA-specific. This BRAM has a
maximum data width of 8 bits, but the output crossbar is configured for 4-bit output mode.
16
IEEE CIRCUITS AND SYSTEMS MAGAZINE
SECOND QUARTER 2021
BLB
WLA
BLA
Wen
BLA
ExtAddr
Local Crossbar
Row Dec. A
WCnfg
Dec.
Row Dec. B
Write Driver
Sense Amplifier

IEEE Circuits and Systems Magazine - Q2 2021

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