IEEE Circuits and Systems Magazine - Q2 2021 - 17

write operations. To simplify timing of the read and write
operations, all modern FPGA BRAMs register all their inputs.
During a write operation, the column decoder activates
the write drivers, which in turn charge the bitlines
(BL and
BL ) according to the input data to-be-written to
the memory cells. Simultaneously, the row decoder activates
the wordline of the row specified by the input write
address, connecting one row of cells to their bitlines so
they are overwritten with new data. During a read operation,
both the BL and BL are pre-charged high and
then the row decoder activates the wordline of the row
specified by the input read address. The contents of the
activated cells cause a slight difference in the voltage between
BL and
BL , which is sensed and amplified by the
sense amplifier circuit to produce the output data [52].
The main architectural decisions in designing FPGA
BRAMs are choosing their capacity, data word width, and
number of read/write ports. More capable BRAMs cost
more silicon area, so architects must carefully balance
BRAM design choices while taking into account the most
common use cases in application circuits. The area occupied
by the SRAM cells grows linearly with the capacity
of the BRAM, but the area of the peripheral circuitry
and the number of routing ports grows sub-linearly. This
means that larger BRAMs have lower area per bit, making
large on-chip buffers more efficient. On the other hand, if
an application requires only small RAMs, much of the capacity
of a larger BRAM may be wasted. Similarly, a BRAM
with a larger data width can provide higher data bandwidth
to downstream logic. However, it costs more area
than a BRAM with the same capacity but a smaller word
width, as the larger data word width necessitates more
sense amplifiers, write drivers and programmable routing
ports. Finally, increasing the number of read/write
ports to a BRAM increases the area of both the SRAM
cells and the peripheral circuitry, but again increases the
data bandwidth the BRAM can provide and allows more
diverse uses. For example, FIFOs (which are ubiquitous
in FPGA designs) require both a read and a write port.
The implementation details of a dual-port SRAM cell is
shown at the bottom of Fig. 12. Implementing a second
port to the SRAM cell (port B highlighted in red) adds
two transistors, increasing the area of the SRAM cells
by 33%. In addition, the second port also needs an additional
copy of the sense amplifiers, write drivers and
row decoders (the " Read/Write Circuitry B " and " Row
Decoder B " blocks in Fig. 12). If both ports are read/write
(r/w), we also have to double the number of ports to the
programmable routing.
Because the FPGA on-chip memory must satisfy the
needs of every application implemented on that FPGA, it
is also common to add extra configurability to BRAMs to
allow them to adapt to application needs [53], [54]. FPGA
SECOND QUARTER 2021
BRAMs are designed to have configurable width and
depth by adding low-cost multiplexing circuitry to the
peripherals of the memory array. For example, in Fig. 12
the actual SRAM array is implemented as a 4 × 8-bit array,
meaning it naturally stores 8-bit data words. By adding
multiplexers controlled by 3 address bits to the output
crossbar, and extra decoding and enabling logic to the
read/write circuitry, this RAM can also operate in 8 × 4-bit,
16 × 2-bit or 32 × 1-bit modes. The width configurability
decoder (WCnfg Dec.) selects between Vdd
and address
bits, as shown in the top-left of Fig. 12 for a maximum
word size of 8 bits. The multiplexers are programmed
using configuration SRAM cells and are used to generate
column select (CS) and write enable (Wen) signals that
control the sense amplifiers and write drivers for narrow
read and write operations, respectively. For typical
BRAM sizes (several kb or more), the cost of this additional
width configurability circuitry is small compared
to the cost of a conventional SRAM array, and it does not
require any additional routing ports.
Another unique component of the FPGA BRAMs compared
to conventional memory blocks is their interface
to the programmable routing fabric. This interface is generally
designed to be similar to that of the logic blocks
described in Section III-A; it is easier to create a routing
architecture that balances flexibility and cost well if all
block types connect to it in similar ways. Connection
block multiplexers, followed by local crossbars in some
FPGAs, form the BRAM input routing ports, while the
read outputs drive switch block multiplexers to form the
output routing ports. These routing interfaces are costly,
particularly for small BRAMs; they constitute 5% to 35%
of the BRAM tile area for 256Kb down to 8Kb BRAMs, respectively
[55]. This motivates minimizing the number
of routing ports to a BRAM as much as possible without
unduly comprising its functionality. Table I summarizes
the number of routing ports required for different numbers
and types of BRAM read and write ports. For example,
a single-port BRAM (1r/w) requires
WD2lo ()g
+
input ports for write data and read/write address, and W
Table I.
Number of routing ports needed for different numbers
and types of BRAM read/write ports (W: data width, D:
BRAM depth).
BRAM Ports BRAM Mode
1r
1r/w
1r+1w
2r/w
2r+2w
Single-port ROM
Single-port RAM
# Routing Ports
log ()D W
log ()D 2W
log ()D +
log ()D +
log ()D +
2
2
2
2
+
+
Simple dual-port RAM 22W
True dual-port RAM 24W
Quad-port RAM
2
44W
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