IEEE Circuits and Systems Magazine - Q2 2021 - 2

Features (continued)
Editor-in-Chief
Yiran Chen, Duke University, USA,
Email: yiran.chen@duke.edu
Deputy Editor-in-Chief
Leibo Liu, Tsinghua University, China
provide faster and more efficient computation. Instead, architectural
improvements are necessary to provide improved performance,
power reduction, and/or reduced cost. Nowhere is this more apparent
than when looking at Deep Learning workloads. Cutting-edge
techniques achieving state-of-the-art training accuracy demand
ever-larger training data-sets and more-complex network topologies,
which results in longer training times. At the same time, after training
these networks, we expect them to be deployed widely. As a result,
executing large networks efficiently becomes critical, whether that
execution is done in a data center or in an embedded system. In this
article, we look at trends in deep learning research that present new
opportunities for domain-specific hardware architectures and explore
how next-generation compilation tools might support them.
97 Synthesizing General-Purpose Code
Into Dynamically Scheduled Circuits
Lana Josipovic´, Andrea Guerrieri, and Paolo Ienne
High-level synthesis (HLS) tools generate hardware designs from
high-level programming languages and should liberate designers from
the details of hardware description languages like VHDL and Verilog.
HLS tools typically build datapaths that are controlled using a centralized
controller, which relies on a compile-time schedule to determine the
clock cycle when each operation executes. Such an approach results
in high-throughput pipelined designs only in cases where memory
accesses are provably independent and critical control decisions are
determinable during code compilation. Unfortunately, when this is not
the case, current tools must make pessimistic assumptions, yielding
inferior schedules and lower performance. Recent advances in
HLS have explored methods to overcome the conservatism in static
scheduling and to remove the inability of HLS tools to handle dynamic
events. Dataflow circuits play a significant role in this context: they
are built out of units that communicate using point-to-point pairs of
handshake control signals and this distributed control mechanism
effectively implements a dynamic schedule, adapted at runtime to
particular memory and control outcomes. Dataflow circuits can exploit
the same optimization opportunities as standard HLS circuits (i.e.,
pipelining and resource sharing), but also introduce to HLS features
similar to those of modern superscalar processors (i.e., out-of-order
memory accesses and speculative execution), which are key for HLS
to be successful in new contexts and broader application domains.
Associate Editors
Mohab Hussein Anis, American University, Egypt
Marco Carli, Università degli Studi 'Roma TRE', Italy
Fan Chen, Indiana University Bloomington, USA
Anthony C Davies, King's College London, UK
Gordana Jovanovic Dolecek, Institute INAOE, Mexico
José E. Franca, University of Lisbon, Portugal
Bah-Hwee Gwee, Nanyang Technological University, Singapore
Liviu Goras, " Gheorghe Asachi " Technical University of Iasi, Romania
Jie Han, University of Alberta, Canada
Chih-Cheng Hsieh, National Tsing Hua University, Taiwan
André Kaup, Friedrich-Alexander University Erlangen-Nürnberg, Germany
Chris Kim, University of Minnesota, USA
Alexander S. Korotkov, Peter the Great St. Petersburg
Polytechnic University, Russia
Zhan Ma, Nanjing University, China
Mahesh Mehendale, Texas Instruments, USA
Nele Mentens, Katholieke Universiteit Leuven, Belgium
Marvin Onabajo, Northeastern University, USA
Jongsun Park, Korea University, Korea
Qinru Qiu, Syracuse University, USA
Ricardo Reis, Federal University of Rio Grande do Sul, Brazil
Branimir Reljin, University of Belgrade, Serbia
Salil Kumar Sanyal, Jadavpur University, India
M. N. S. Swamy, Concordia University, Canada
Chao Wang, Huazhong University of Science and Technology, China
Wujie Wen, Lehigh University, USA
Shigeru Yamashita, Ritsumeikan University, Japan
Xuan Zhang, Washington University in St. Louis, USA
Departments
3 From the Guest Editors
120 CAS Society News
128 Correction
Scope: The magazine covers the subject areas represented by the Society's transactions, including:
analog, passive, switch capacitor, and digital filters; electronic circuits, networks, graph theory, and RF
communication circuits; system theory; discrete, IC, and VLSI circuit design; multidimensional circuits and
systems; large-scale systems and power networks; nonlinear circuits and systems, wavelets, filter banks,
and applications; neural networks; and signal processing. Content also covers the areas represented by
the Society technical committees: analog signal processing, cellular neural networks and array computing,
circuits and systems for communications, computer-aided network design, digital signal processing,
multimedia systems and applications, neural systems and applications, nonlinear circuits and systems,
power systems and power electronics and circuits, sensors and micromaching, visual signal processing
and communication, and VLSI systems and applications. Lastly, the magazine covers the interests
represented by the widespread conference activity of the IEEE Circuits and Systems Society. In addition
to the technical articles, the magazine also covers Society administrative activities, as for instance the
meetings of the Board of Governors, Society People, as for instance the stories of award winners-fellows,
medalists, and so forth, and Places reached by the Society, including readable reports from the Society's
conferences around the world.
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2
IEEE CIRCUITS AND SYSTEMS MAGAZINE
SECOND QUARTER 2021

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IEEE Circuits and Systems Magazine - Q2 2021

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