IEEE Circuits and Systems Magazine - Q2 2021 - 31

data centers around the world. Still, the integration of big data
analytics frameworks with heterogeneous hardware components
such as GPGPUs and FPGAs is challenging, because
there is an increasing gap in the level of abstraction between
analytics solutions developed with big data analytics frameworks,
and accelerated kernels developed with heterogeneous
components. In this article, we focus on FPGA accelerators that
have seen wide-scale deployment in large cloud infrastructures.
FPGAs allow the implementation of highly optimized hardware
architectures, tailored exactly to an application, and unburdened
by the overhead associated with traditional general-purpose
computer architectures. FPGAs implementing dataflow-oriented
architectures with high levels of (pipeline) parallelism can provide
high application throughput, often providing high energy
efficiency. Latency-sensitive applications can leverage FPGA
accelerators by directly connecting to the physical layer of a network,
and perform data transformations without going through
the software stacks of the host system. While these advantages
of FPGA accelerators hold promise, difficulties associated with
programming and integration limit their use. This article explores
the existing practices in big data analytics frameworks,
discusses the aforementioned gap in development abstractions,
and provides some perspectives on how to address these challenges
in the future.
I. Introduction
A
lot has changed in the world of analytics since the
first database management systems were popularized.
Highly structured data was carefully
administered, making it easy to distill information. Now,
the field is confronted with a quintuple challenge: more
data to process, more abstraction desired, new computationally
intensive paradigms (like AI), and more latency
sensitive (interactive) uses. At the same time, transistor
performance improvements are slowing down and power
efficiency becomes a greater and greater challenge.
Meanwhile, recent developments have also presented
us with several new opportunities. Cloud infrastructure
has opened up the use of large compute clusters
to a far wider range of users by allowing more efficient
sharing of hardware. Highly efficient compute units
have been designed to target certain workloads in a
highly specialized manner. The memory hierarchy has
been extended with solid state drives and storage class
memory, improving both throughput and latency for
access to large datasets. Similarly, networking technology
has been advancing rapidly, still keeping pace with
Moore's law.
While the performance increase of general-purpose
CPUs is not able to keep up with the advances in their
periphery, reconfigurable logic found in FPGAs provides
several unique strengths that may be able to cope
better. For many applications, FPGAs have the ability to
transform and filter data at the very high data rates that
new storage systems can provide. When attached directly
to the network, reconfigurable logic can provide
similar functionality at line-rate with very low latency,
SECOND QUARTER 2021
because data no longer needs to traverse various software
layers of the networking and application stack. It
allows users to specialize FPGA accelerators found in
cloud instances to their applications, without the need
to replace hardware. Tailoring the logic mapped on top
of the FPGA fabric allows the construction of custom
dataflow computers, where there is a minimal need to
move data back and forth through the memory hierarchy.
Even in cases where such FPGA designs provide
only marginal gains in terms of throughput, the computations
tend to be more power-efficient because of the
reduced data movement and because the FPGA operates
at relatively low clock frequencies.
However, FPGA acceleration still has several challenges.
In spite of efforts to improve the ease of programming,
FPGAs are currently not yet suitable to be used
directly by an audience untrained in circuit design. Very
few people with proper hardware design training are
also active in the field of big data analytics, leading to a
scarcity of designers. Furthermore, the use of FPGAs in
cloud instances is currently still very explicit, requiring
FPGA-aware code paths. Also, data coming from highlevel
languages running on interpreters and virtual machines
needs to be transformed and copied sometimes
several times during (de)serialization before it can be
used in the accelerator. This often negates any advantage
that can be gained by designing the accelerator in
the first place. Last, there is still no systematic way to address
the long synthesis time for datacenter-class FPGAs
(where 12 hours is no exception) and the relatively long
reprogramming delay (in the order of 100 ms).
In this article, we investigate these challenges and opportunities
and summarize recent progress, and lay out
a roadmap for further improvement. Ultimately, our goal
is seamless integration of FPGAs in cloud infrastructure
for big data analytics. Section II presents a more in-depth
background of the related topics. Then, Section III discusses
recent developments (opportunities) and missing
links (challenges) for near-future big data analytics
systems. Section IV presents a prototype system that
features many of the components discussed. Section V
provides an analysis and evaluation of our prototype implementation.
Section VI provides a discussion of related
work. Finally, Section VII concludes the article.
II. Background
A. Heterogeneous Computing
Increases in single-thread performance have dropped to
less than 10% per year during the last decade [1] due in
part to a slowdown in Moore's law. The additional transistors
are not directly translating into raw performance
anymore, but instead into higher core counts and, more
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IEEE Circuits and Systems Magazine - Q2 2021

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