IEEE Circuits and Systems Magazine - Q2 2021 - 35

application, the data should be represented the same
way in memory. This way, data does not need to be (de)
serialized when passed between different software technologies
(e.g. Java and Python).
In addition, the format uses a column-oriented layout
as opposed to the row-oriented layout used in traditional
systems. Although the choice to organize tables
in a row- or column-oriented fashion has pros and cons
depending on the way it is accessed (e.g. retrieving a
full row of data is very efficient using a row-oriented
format, but requires several random memory accesses
in a columnar format), in the context of data analytics
storing the data in a columnar format where data of
the same type is stored contiguously has a number of
advantages [18]. The first advantage is that this allows
computations on this data to take advantage of SIMD
instructions that are supported in most contemporary
hardware. Several values are loaded into wide SIMD
registers in the CPU, after which operations can be
performed on all of them simultaneously using a single
instruction. The Gandiva execution engine that targets
Arrow-formatted data makes use of the LLVM compiler
framework to generate highly optimized SIMD code for
CPUs using JIT compilation.
The second advantage of using a columnar format is
that it allows to send buffers of data containing a column
of values of the same type to accelerators such
as GPUs and FPGAs. This allows these columns to be
streamed into functional units in a straightforward
fashion, without the need for decoding values from a
row-oriented buffer of entries that can contain complex,
nested and even variable-length datatypes. Whereas
row-oriented formats continue to be commonplace in
transactional systems (that need to process frequent
record updates), analytics systems tend to work in a
column-oriented fashion.
To summarize, Apache Arrow not only facilitates interoperability
between software, but also between different
types of compute hardware.
Table I.
Key system properties.
Hardware
III. Opportunities and Challenges
In our view, the success of an analytics system in the
near future will revolve around leveraging a number of
key properties listed in Table I. In the following sections,
we will discuss recent developments in the areas of
Hardware, Programming and Runtime, that we believe
will provide opportunities for building these systems.
Then, we will provide views on current efforts to address
challenges or missing links in the field.
A. Opportunities: Recent Developments in
Big Data Analytics Systems
1) Hardware
In the area of computer hardware, recent developments
have included several new components and interconnect
technologies that will allow executing parts of the
workload in the location and compute fabric that are
most suitable for it.
Heterogeneous Compute Fabrics
In addition to the general-purpose GPU offerings that have
become popular in recent years, FPGA-based datacenter
accelerator cards have been introduced that can be integrated
into existing servers [4]. In the near future, these
accelerators will contain several types of compute fabric,
including not only reconfigurable logic but also digital signal
processing units, scalar processors and a grid of VLIW
processors connected by a Network-on-Chip [19].
FPGA Overlays
As synthesis can take several hours especially for larger
FPGAs, using a programmable overlay can provide
a middle ground between performance and compilation
time. An overlay is a fixed FPGA design containing
compute elements that are highly optimized for a specific
application or application domain. These elements
can be programmed, and are typically supported by a
compiler or other tool-chain that does not require
* Heterogeneous (various types of compute fabric)
* Uniform memory access
* Accelerated storage and networking
Programming * Spatial (functional, declarative, etc.) programming paradigms
* Graph representation (DAG) of the application should be scheduled optimally for the (heterogeneous) hardware
* Allow easy integration of user-designed accelerators
* Allow acceleration using IP libraries
* A single common representation of data in memory (no serialization)
Runtime
* Monitor performance of running tasks
* Optimize performance by 1) synthesizing new components and storing them in the IP library, 2) updating
parameters of accelerators according to the changing data characteristics
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IEEE Circuits and Systems Magazine - Q2 2021

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